diff -uNr linux-2.4.31/drivers/video/Config.in linux-fb/drivers/video/Config.in
--- linux-2.4.31/drivers/video/Config.in	2004-02-18 14:36:31.000000000 +0100
+++ linux-fb/drivers/video/Config.in	2005-10-13 17:54:00.000000000 +0200
@@ -159,6 +159,13 @@
 	    bool '    SIS 300 series support' CONFIG_FB_SIS_300
 	    bool '    SIS 315/330 series support' CONFIG_FB_SIS_315
 	 fi
+	 tristate '  National Geode display support (EXPERIMENTAL)' CONFIG_FB_GEODE 
+	 if [ "$CONFIG_FB_GEODE" != "n" ]; then
+	    bool '    TV Support' CONFIG_FB_GEODE_TV
+	    bool '    FlatPanel Support' CONFIG_FB_GEODE_FP
+	    bool '    DDC Support' CONFIG_FB_GEODE_DDC
+	    bool '    GAL Support' CONFIG_FB_GEODE_GAL
+	 fi 
 	 tristate '  NeoMagic display support (EXPERIMENTAL)' CONFIG_FB_NEOMAGIC
 	 tristate '  3Dfx Banshee/Voodoo3 display support (EXPERIMENTAL)' CONFIG_FB_3DFX
 	 tristate '  3Dfx Voodoo Graphics (sst1) support (EXPERIMENTAL)' CONFIG_FB_VOODOO1
@@ -312,7 +319,7 @@
 	   "$CONFIG_FB_TX3912" = "y" -o \
 	   "$CONFIG_FB_SIS" = "y" -o "$CONFIG_FB_NEOMAGIC" = "y" -o \
 	   "$CONFIG_FB_STI" = "y" -o "$CONFIG_FB_HP300" = "y" -o \
-	   "$CONFIG_FB_INTEL" = "y" ]; then
+	   "$CONFIG_FB_INTEL" = "y" -o "$CONFIG_FB_GEODE" = "y" ]; then
 	 define_tristate CONFIG_FBCON_CFB8 y
       else
 	 if [ "$CONFIG_FB_ACORN" = "m" -o "$CONFIG_FB_ATARI" = "m" -o \
@@ -335,7 +342,7 @@
 	      "$CONFIG_FB_RADEON" = "m" -o "$CONFIG_FB_INTEL" = "m" -o \
 	      "$CONFIG_FB_SA1100" = "m" -o "$CONFIG_FB_SIS" = "m" -o \
 	      "$CONFIG_FB_TX3912" = "m" -o "$CONFIG_FB_NEOMAGIC" = "m" -o \
-	      "$CONFIG_FB_STI" = "m" -o "$CONFIG_FB_INTEL" = "m" ]; then
+	      "$CONFIG_FB_STI" = "m" -o "$CONFIG_FB_INTEL" = "m"  -o "$CONFIG_FB_GEODE" = "m" ]; then
 	    define_tristate CONFIG_FBCON_CFB8 m
 	 fi
       fi
@@ -354,7 +361,7 @@
 	   "$CONFIG_FB_CYBER2000" = "y" -o "$CONFIG_FB_3DFX" = "y"  -o \
 	   "$CONFIG_FB_SIS" = "y" -o "$CONFIG_FB_SA1100" = "y" -o \
 	   "$CONFIG_FB_PVR2" = "y" -o "$CONFIG_FB_VOODOO1" = "y" -o \
-	   "$CONFIG_FB_NEOMAGIC" = "y" -o "$CONFIG_FB_INTEL" = "y" ]; then
+	   "$CONFIG_FB_NEOMAGIC" = "y" -o "$CONFIG_FB_INTEL" = "y" -o "$CONFIG_FB_GEODE" = "y" ]; then
 	 define_tristate CONFIG_FBCON_CFB16 y
       else
 	 if [ "$CONFIG_FB_ATARI" = "m" -o "$CONFIG_FB_ATY" = "m" -o \
@@ -372,7 +379,7 @@
 	      "$CONFIG_FB_SA1100" = "m" -o "$CONFIG_FB_RADEON" = "m" -o \
 	      "$CONFIG_FB_INTEL" = "m" -o \
 	      "$CONFIG_FB_PVR2" = "m" -o "$CONFIG_FB_VOODOO1" = "m" -o \
-	      "$CONFIG_FB_NEOMAGIC" = "m" -o "$CONFIG_FB_INTEL" = "m" ]; then
+	      "$CONFIG_FB_NEOMAGIC" = "m" -o "$CONFIG_FB_INTEL" = "m" -o "$CONFIG_FB_GEODE" = "m" ]; then
 	    define_tristate CONFIG_FBCON_CFB16 m
 	 fi
       fi
diff -uNr linux-2.4.31/drivers/video/Makefile linux-fb/drivers/video/Makefile
--- linux-2.4.31/drivers/video/Makefile	2004-02-18 14:36:31.000000000 +0100
+++ linux-fb/drivers/video/Makefile	2005-10-13 17:50:36.000000000 +0200
@@ -119,6 +119,11 @@
 obj-y				  += sis/sisfb.o
 endif
 
+subdir-$(CONFIG_FB_GEODE)		  += nsc
+ifeq ($(CONFIG_FB_GEODE),y)
+obj-y				  += nsc/nsc.o
+endif
+
 subdir-$(CONFIG_FB_ATY)		  += aty
 ifeq ($(CONFIG_FB_ATY),y)
 obj-y				  += aty/atyfb.o
diff -uNr linux-2.4.31/drivers/video/fbmem.c linux-fb/drivers/video/fbmem.c
--- linux-2.4.31/drivers/video/fbmem.c	2005-06-01 02:56:56.000000000 +0200
+++ linux-fb/drivers/video/fbmem.c	2005-10-13 17:50:36.000000000 +0200
@@ -122,6 +122,8 @@
 extern int tridentfb_setup(char*);
 extern int sisfb_init(void);
 extern int sisfb_setup(char*);
+extern int nscfb_init(void);
+extern int nscfb_setup(char*);
 extern int stifb_init(void);
 extern int stifb_setup(char*);
 extern int pmagaafb_init(void);
@@ -240,6 +242,9 @@
 	{ "sst", sstfb_init, sstfb_setup },
 #endif
 
+#ifdef CONFIG_FB_GEODE
+    { "nscfb", nscfb_init, nscfb_setup },
+#endif
 	/*
 	 * Generic drivers that are used as fallbacks
 	 * 
@@ -504,11 +509,6 @@
 	if (! fb)
 		return -ENODEV;
 	switch (cmd) {
-	case FBIOGET_VSCREENINFO:
-		if ((i = fb->fb_get_var(&var, PROC_CONSOLE(info), info)))
-			return i;
-		return copy_to_user((void *) arg, &var,
-				    sizeof(var)) ? -EFAULT : 0;
 	case FBIOPUT_VSCREENINFO:
 		if (copy_from_user(&var, (void *) arg, sizeof(var)))
 			return -EFAULT;
diff -uNr linux-2.4.31/drivers/video/nsc/Makefile linux-fb/drivers/video/nsc/Makefile
--- linux-2.4.31/drivers/video/nsc/Makefile	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/Makefile	2005-10-13 18:13:24.000000000 +0200
@@ -0,0 +1,44 @@
+# <LIC_AMD_STD>
+# Copyright (c) 2004 Advanced Micro Devices, Inc.
+# 
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+# 
+# The full GNU General Public License is included in this distribution in the
+# file called COPYING
+# </LIC_AMD_STD>
+# <CTL_AMD_STD>
+# </CTL_AMD_STD>
+# <DOC_AMD_STD>
+# </DOC_AMD_STD>
+#
+# Makefile for the Geode framebuffer driver
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+#
+# Note 2! The CFLAGS definitions are now in the main makefile...
+
+export-objs    := fbgen.o
+
+O_TARGET := nsc.o
+EXTRA_CFLAGS := -I./gfx -I./panel -I./ddc  -DOS_LINUX 
+
+obj-y   := nsc_fb.o durango.o panel.o ddc.o nsc_ioctl.o nsc_gx1_fb.o fbgen.o nsc_gx2_fb.o
+
+obj-m   := $(O_TARGET)
+
+include $(TOPDIR)/Rules.make
+
diff -uNr linux-2.4.31/drivers/video/nsc/ddc/ddc.c linux-fb/drivers/video/nsc/ddc/ddc.c
--- linux-2.4.31/drivers/video/nsc/ddc/ddc.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/ddc/ddc.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,67 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * File Contents: This file contains the function prototypes and macro  
+ *                definitions.
+ *
+ * SubModule:     Display Data Channel support.
+ * </DOC_AMD_STD>
+ */
+
+#if defined(linux) /* Linux */
+#ifdef __KERNEL__
+#include <linux/string.h>
+#include <asm/io.h> 
+#else
+#include <linux/fs.h>
+#include <asm/mman.h>
+
+/* #include <asm/fcntl.h> */
+#endif /* __KERNEL__ */
+#elif defined(_WIN32) /* windows */
+#include <windows.h>
+#endif 
+
+/* TODO: generalize debug messages */
+/* undefine the retail message when not CE */
+#if !defined(_WIN32_WCE)
+#define RETAILMSG(_F, _PARA )
+#endif
+
+#include "ddc.h"
+#include "gfx_defs.h" 
+/*These variables are global and intiallized by init routines*/
+extern unsigned char *gfx_virt_regptr;
+extern unsigned char *gfx_virt_fbptr;
+extern unsigned char *gfx_virt_vidptr;
+extern unsigned char *gfx_virt_vipptr;
+
+#define PLATFORM_DYNAMIC	1	/* runtime selection */
+#define PLATFORM_5530		1   /* 5530 based platforms */
+#define PLATFORM_x200		1   /* x200 based with ddc on gpio */
+
+
+/* This include file included to handle the ddc protocols */
+#include "ddc_init.c"
+
diff -uNr linux-2.4.31/drivers/video/nsc/ddc/ddc.h linux-fb/drivers/video/nsc/ddc/ddc.h
--- linux-2.4.31/drivers/video/nsc/ddc/ddc.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/ddc/ddc.h	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,55 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * File Contents: This file contains the file inclusions,function prototypes and  
+ *                macro	definitions.
+ *
+ * SubModule:     Display Data Channel support.
+ * </DOC_AMD_STD>
+ */
+
+
+#ifndef _ddc_h
+#define _ddc_h
+
+#include "gfx_rtns.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* prototypes */
+void ddc_init(void);
+void ddc_cleanup(void);
+void nextFromList(unsigned long *xres, unsigned long *yres, unsigned long *hz);
+extern int gfx_video_type;
+extern unsigned char gfx_inb(unsigned short port);
+extern unsigned long gfx_ind(unsigned short port);
+extern void gfx_outb(unsigned short port, unsigned char data);
+extern void gfx_outd(unsigned short port, unsigned long data);
+#ifdef __cplusplus
+}
+#endif
+#endif /* !_ddc_h */
+
+/* END OF FILE */
diff -uNr linux-2.4.31/drivers/video/nsc/ddc/ddc_5530.c linux-fb/drivers/video/nsc/ddc/ddc_5530.c
--- linux-2.4.31/drivers/video/nsc/ddc/ddc_5530.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/ddc/ddc_5530.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,430 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * File Contents: This file contains the function definitions to access the  
+ *                CS5530  I/O compaion.
+ *
+ * SubModule:     Display Data Channel support.
+ * </DOC_AMD_STD>
+ */
+
+
+#include "ddc_5530.h"
+#include "gfx_regs.h"
+
+/*----------------------------------------------------------------------------
+ * init_5530:
+ *
+ * Description	  : This function is called to configure the DDC Serial Data
+ *                    line to probe the monitor.
+ *
+ * Parameters     : None
+ *
+ * Returns		  : None
+ *
+ * Comments       : This function  should be invoked before readbyte or write
+ *                   byte routines.
+*----------------------------------------------------------------------------
+*/
+void init_5530()
+{
+	RETAILMSG( 0,(TEXT("setup\n")));
+	SetSDA_5530();    /* this function connfigure data line */
+	WaitSCLHigh();    /* Waiting for Serial Clock Line go high*/
+	ClearSCL_5530();  /*  Clearing the clock line */
+	WaitSCLHigh();
+	ClearSCL_5530();
+	WaitSCLHigh();
+	requestData_5530(); /* sending the data request */
+	ReadByte_5530(0);   /* Read the monitor data */
+	StopBit_5530();     /* Setting the stop bit */
+}
+
+/*----------------------------------------------------------------------------
+ * ReadByte_5530
+ *
+ * Description	  : This function reads the data bit by bit and setting ack
+ *                  after the one byte read.
+ *
+ * Parameters.
+ *       ack      : Gets the one byte data.
+ * Returns		  : Returning one byte information after read bit.
+ *
+ * Comments       : This function  should be invoked before readbyte or write
+ *                  byte routines.
+*----------------------------------------------------------------------------
+*/
+unsigned char ReadByte_5530(int ack)
+{
+	unsigned char val = 0;
+	int i;
+	RETAILMSG( 0,(TEXT("getByte\n")));
+	for (i = 0; i < 8; i++) {
+		val <<= 1;
+		val |= ReadBit();
+	}
+
+	Ack_5530(ack);
+	return val;
+}
+
+/*---------------------------------------------------------------------------
+ * StartBit_5530
+ *
+ * Description	  : This function sending out the start bit of serial data
+ *
+ *
+ * Parameters     : None
+ *
+ * Returns		  : None
+ *
+ * Comments       : This function indicates the begining ddc seiral data.
+ *
+*----------------------------------------------------------------------------
+*/
+void StartBit_5530()
+{
+	RETAILMSG( 0,(TEXT("startBit\n")));
+	wait(DEFAULTDELAY);
+	SetSDA_5530();
+	wait(DEFAULTDELAY);
+	WaitSCLHigh();
+	wait(DEFAULTDELAY);
+	ClearSDA_5530();
+	wait(DEFAULTDELAY);
+}
+
+/*---------------------------------------------------------------------------
+ * StopBit_5530.
+ *
+ * Description	  : This function sending out the stop bit of serial data
+ *
+ *
+ * Parameters     : None
+ *
+ * Returns		  : None
+ *
+ * Comments       : This function indicates the end ddc seiral data.
+ *
+*----------------------------------------------------------------------------
+*/
+void StopBit_5530()
+{
+	RETAILMSG( 0,(TEXT("stopBit\n")));
+	wait(DEFAULTDELAY);
+	WaitSCLHigh();
+	wait(DEFAULTDELAY);
+	SetSDA_5530();
+	wait(2);
+}
+
+/*---------------------------------------------------------------------------
+ * Ack_5530:
+ *
+ * Description	  : This sends out the ack data
+ *
+ * Parameters     :
+ *        flag    : Value read in ReaByte routine is passed
+ * Returns		  : None
+ *
+ * Comments       : None
+*----------------------------------------------------------------------------
+*/
+void Ack_5530(int flag)
+{
+	RETAILMSG( 0,(TEXT("ACK\n")));
+	wait(DEFAULTDELAY);
+	ClearSCL_5530();
+	wait(DEFAULTDELAY);
+	if (flag) {
+		ClearSDA_5530();
+	} else {
+		SetSDA_5530();
+	}
+	WaitSCLHigh();
+	ClearSCL_5530();
+	wait(DEFAULTDELAY);
+	SetSDA_5530();
+	RETAILMSG( 0,(TEXT("ACK Exit\n")));
+}
+
+/*---------------------------------------------------------------------------
+ * waitForAck:
+ *
+ * Description	  : This routine waits the ack SDL data.
+ *
+ * Parameters     : none
+ *
+ * Returns		  : None
+ *
+ * Comments       : None
+*----------------------------------------------------------------------------
+*/
+int waitForAck_5530()
+{
+	unsigned long target=0;
+	int i = 0;
+
+	RETAILMSG( 0,(TEXT("waitForACK\n")));
+	wait(DEFAULTDELAY);
+	ClearSCL_5530();
+	wait(DEFAULTDELAY);
+	SetSDA_5530();
+
+#ifndef _WIN32_WCE
+	/* Do this for two times (2 uSec) */
+	for (i=0; i<2; i++) {
+		wait(DEFAULTDELAY);
+		if (GetSDA_5530() == 0) {
+			wait(DEFAULTDELAY);
+			WaitSCLHigh();
+			return 1;
+		} 
+	}
+	/* Time Out */
+	wait(DEFAULTDELAY);
+	WaitSCLHigh();
+	return 0;
+#else
+	target = GetTickCount() + 2;
+	for (;;) {
+		wait(DEFAULTDELAY);
+		if (GetSDA_5530() == 0) 
+		{
+			wait(DEFAULTDELAY);
+			WaitSCLHigh();
+			return 1;
+	    /* } else if(endtime > target) { */
+		} else if(GetTickCount() > target) 
+		{
+			wait(DEFAULTDELAY);
+			WaitSCLHigh();
+			return 0;
+		}
+	}
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * requestData.
+ *
+ * Description		: This routine request the data and configure SDA to Rx mode.
+ *
+ * Parameters		: None   
+ *
+ * Returns			: None
+ *
+ * Comments         : None
+*----------------------------------------------------------------------------
+*/
+
+void requestData_5530() 
+{
+	RETAILMSG( 0,(TEXT("requestData\n")));
+	StartBit_5530();
+	SendByte(0xa0);
+	SendByte(0);
+	StopBit_5530();
+
+	StartBit_5530();
+	SendByte(0xa1);
+}
+
+/***************************************************************
+* H/W DEPENDENT LOW LAYER ROUTINES
+***************************************************************/
+/*---------------------------------------------------------------------------
+ * startXfer_5530.
+ *
+ * Description	  : This routine is called to sets SDA to high state when the
+ *                    transfer starts.
+ * Parameters     : None
+ * Returns		  : None
+ *
+ * Comments       : SCL should be high when toggling.
+*----------------------------------------------------------------------------
+*/
+void startXfer_5530()
+{
+	unsigned long data = READ_VID32(CS5530_DISPLAY_CONFIG);
+	RETAILMSG( 0,(TEXT("startXfer\n")));
+	data &= ~CS5530_DCFG_DDC_SCL;
+	WRITE_VID32(CS5530_DISPLAY_CONFIG, data);
+	data &= ~CS5530_DCFG_DDC_SDA;
+	WRITE_VID32(CS5530_DISPLAY_CONFIG, data);
+	data |= CS5530_DCFG_DDC_SCL;
+	WRITE_VID32(CS5530_DISPLAY_CONFIG, data);
+	data |= CS5530_DCFG_DDC_SDA;
+	WRITE_VID32(CS5530_DISPLAY_CONFIG, data);
+}
+/*---------------------------------------------------------------------------
+ * endXfer_5530.
+ *
+ * Description	  : This routine is called to sets SDA to low state when the
+ *                  transfer ends.
+ *
+ * Parameters     : None
+ * Returns		  : None
+ *
+ * Comments       : SCL should be high when toggling.
+*----------------------------------------------------------------------------
+*/
+
+void endXfer_5530() 
+{
+	unsigned long data = READ_VID32(CS5530_DISPLAY_CONFIG);
+	RETAILMSG( 0,(TEXT("endXfer\n")));
+	data &= ~CS5530_DCFG_DDC_SCL;
+	WRITE_VID32(CS5530_DISPLAY_CONFIG, data);
+	data |= CS5530_DCFG_DDC_SDA;
+	WRITE_VID32(CS5530_DISPLAY_CONFIG, data);
+	data |= CS5530_DCFG_DDC_SCL;
+	WRITE_VID32(CS5530_DISPLAY_CONFIG, data);
+	data &= ~CS5530_DCFG_DDC_SDA;
+	WRITE_VID32(CS5530_DISPLAY_CONFIG, data);
+}
+
+/*---------------------------------------------------------------------------
+ * SetSCL_5530.
+ *
+ * Description	  : This routine sets the serial clock line to high.
+ *
+ *
+ * Parameters     : None
+ * Returns		  : None
+ *
+ * Comments       : none
+*----------------------------------------------------------------------------
+*/
+void SetSCL_5530() 
+{
+	unsigned long data = READ_VID32(CS5530_DISPLAY_CONFIG);
+	RETAILMSG( 0,(TEXT("SetSCL\n")));
+	data |= CS5530_DCFG_DDC_SCL;
+	WRITE_VID32(CS5530_DISPLAY_CONFIG, data);
+}
+
+/*---------------------------------------------------------------------------
+ * ClearSCL_5530.
+ *
+ * Description	  : This routine sets the serial clock line to low.
+ *
+ *
+ * Parameters     : None
+ * Returns		  : None
+ *
+ * Comments       : none
+*----------------------------------------------------------------------------
+*/
+void ClearSCL_5530() 
+{
+	unsigned long data = READ_VID32(CS5530_DISPLAY_CONFIG);
+	data &= ~CS5530_DCFG_DDC_SCL;
+	RETAILMSG( 0,(TEXT("DDCclockLo %X\n"),data));
+	WRITE_VID32(CS5530_DISPLAY_CONFIG, data);
+}
+
+/*---------------------------------------------------------------------------
+ * GetSCL_5530.
+ *
+ * Description	  : This routine gets the of SCL data .
+ *
+ *
+ * Parameters     : None
+ * Returns		  : returns SCL data.
+ *
+ * Comments       : none
+*----------------------------------------------------------------------------
+*/
+int GetSCL_5530()
+{
+	unsigned long data = READ_VID32(CS5530_DISPLAY_CONFIG);
+	RETAILMSG( 0,(TEXT("GetSCL %X\n"), data));
+	return ((data & CS5530_DCFG_DDC_SCL) >> 22);
+}
+
+/*---------------------------------------------------------------------------
+ * SetSDA_5530.
+ *
+ * Description	  : This routine sets the serial data line to high.
+ *
+ *
+ * Parameters     : None
+ * Returns		  : None
+ *
+ * Comments       : none
+*----------------------------------------------------------------------------
+*/
+void SetSDA_5530() 
+{
+	unsigned long data = READ_VID32(CS5530_DISPLAY_CONFIG);
+	data |= CS5530_DCFG_DDC_SDA | CS5530_DCFG_DDC_OE;
+	RETAILMSG( 0,(TEXT("SetSDA %X\n"), data));
+	WRITE_VID32(CS5530_DISPLAY_CONFIG, data);
+}
+
+/*---------------------------------------------------------------------------
+ * ClearSDA_5530.
+ *
+ * Description	  : This routine sets the serial data line to low.
+ *
+ *
+ * Parameters     : None
+ * Returns		  : None
+ *
+ * Comments       : none
+*----------------------------------------------------------------------------
+*/
+void ClearSDA_5530()
+{
+	unsigned long data = READ_VID32(CS5530_DISPLAY_CONFIG);
+	data &= ~CS5530_DCFG_DDC_SDA; 
+	data |= CS5530_DCFG_DDC_OE;
+	RETAILMSG( 0,(TEXT("ClearSDA %X\n"), data));
+	WRITE_VID32(CS5530_DISPLAY_CONFIG, data);
+}
+
+/*---------------------------------------------------------------------------
+ * GetSDA_5530.
+ *
+ * Description	  : This routine gets the of SDL data .
+ *
+ *
+ * Parameters     : None
+ * Returns		  : returns SCL data.
+ *
+ * Comments       : none
+*----------------------------------------------------------------------------
+*/
+
+int GetSDA_5530() 
+{
+	unsigned long data = READ_VID32(CS5530_DISPLAY_CONFIG);
+	data &= ~CS5530_DCFG_DDC_OE;
+	WRITE_VID32(CS5530_DISPLAY_CONFIG, data);
+	wait(2); /* 10 */
+	data = READ_VID32(CS5530_DISPLAY_CONFIG);
+	RETAILMSG( 0,(TEXT("GetSDA 0x%8X\n"), data));
+	return (data >> 31);
+}
diff -uNr linux-2.4.31/drivers/video/nsc/ddc/ddc_5530.h linux-fb/drivers/video/nsc/ddc/ddc_5530.h
--- linux-2.4.31/drivers/video/nsc/ddc/ddc_5530.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/ddc/ddc_5530.h	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,54 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * File Contents: This file contains the function prototypes  and macro   
+ *                definition to access the  CS5530  I/O compaion.
+ *
+ * SubModule:     Display Data Channel support.
+
+ * </DOC_AMD_STD>
+ */
+
+#ifndef _ddc_5530_h
+#define _ddc_5530_h
+
+	void init_5530(void);
+	unsigned char ReadByte_5530(int);
+	void StartBit_5530(void);
+	void StopBit_5530(void);
+	void Ack_5530(int);
+	int waitForAck_5530(void);
+	void requestData_5530(void);
+	void startXfer_5530(void);
+	void endXfer_5530(void);
+	void SetSCL_5530(void);
+	void ClearSCL_5530(void);
+	void ClearSDA_5530(void);
+	void SetSDA_5530(void);
+	int GetSDA_5530(void);
+	int GetSCL_5530(void);
+
+#endif /* !_ddc_5530_h */
+
+/* END OF FILE */
diff -uNr linux-2.4.31/drivers/video/nsc/ddc/ddc_defs.h linux-fb/drivers/video/nsc/ddc/ddc_defs.h
--- linux-2.4.31/drivers/video/nsc/ddc/ddc_defs.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/ddc/ddc_defs.h	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,112 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * File Contents: This file contains the macro definitions and data structure  
+ *                definitions of DDC.  
+ * 			
+ * SubModule:     Display Data Channel support.
+ * </DOC_AMD_STD>
+ */
+
+
+#ifndef _ddc_defs_h
+#define _ddc_defs_h
+
+typedef struct _Predefined_DDC{
+	unsigned long xres;
+	unsigned long yres;
+	unsigned long hz;
+}Predefined_DDC;
+
+#define	DEFAULTDELAY	1	/* 1 mSec */
+
+/* Data locations in VESA/EDID ver1.3 format containg 128 Bytes */
+#define VESA1_VERSION 12
+#define VESA1_REVSION 13
+#define VESA1_EST_TIM1 35
+#define VESA1_EST_TIM2 36
+#define VESA1_EST_MANU_TIM 37
+#define VESA1_EST_STAND_TIM 38
+
+/* defines the predefined modes */
+
+Predefined_DDC EstTim1[8] ={
+	{800, 600, 60},
+	{800, 600, 56},
+	{640, 480, 75},
+	{640, 480, 72},
+	{640, 480, 67},
+	{640, 480, 60}, 
+	{720, 400, 88}, 
+	{720, 400, 70}
+};  
+Predefined_DDC EstTim2[8] ={
+	{1280, 1024, 75},
+	{1024, 768, 75}, 
+	{1024, 768, 70}, 
+	{1024, 768, 60}, 
+	{1024, 768, 87}, 
+	{832, 624, 75},  
+	{800, 600, 75},
+	{800, 600, 72}
+};
+Predefined_DDC MfgTim2[1] ={
+	{1152, 870, 75} 
+};
+
+typedef struct _DispAspectRatio{
+	int xRatio;
+	int yRatio;
+}DispAspectRatio;
+
+static DispAspectRatio asp[4] = {
+	{1, 1},
+	{4, 3},
+	{5, 4},
+	{16, 9}
+};
+static unsigned char EDID_Header[8] = {
+	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00};
+
+typedef struct _Platform_DDC_ops {
+	void (*init)(void);
+	unsigned char (*ReadByte)(int);
+	void (*StartBit)(void);
+	void (*StopBit)(void);
+	void (*Ack)(int);
+	int (*waitForAck)(void);
+	void (*requestData)(void);
+	void (*startXfer)(void);
+	void (*endXfer)(void);
+	void (*SetSCL)(void);
+	void (*ClearSCL)(void);
+	void (*ClearSDA)(void);
+	void (*SetSDA)(void);
+	int (*GetSDA)(void);
+	int (*GetSCL)(void);
+} Platform_DDC_ops;
+
+#endif /* !_ddc_defs_h */
+
+/* END OF FILE */
diff -uNr linux-2.4.31/drivers/video/nsc/ddc/ddc_init.c linux-fb/drivers/video/nsc/ddc/ddc_init.c
--- linux-2.4.31/drivers/video/nsc/ddc/ddc_init.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/ddc/ddc_init.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,581 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * File Contents: This file contains the DDC initialization function 
+ *                definitions. 
+ *  
+ * SubModule:     Display Data Channel support.
+ * </DOC_AMD_STD>
+ */
+
+#include "ddc.h"
+#include "ddc_defs.h"
+
+#define DisplayDataLength 128
+#define MAX_MODES 50
+
+/*Forward prototype declarations */
+static unsigned long displaySupports;
+static unsigned char displayData[DisplayDataLength];
+static void WaitSCLHigh(void);
+static void getBlock(unsigned char *, int);
+static void wait(int uSec);
+static int  ReadBit(void);
+static void SendBit(int);
+static void SendByte(unsigned char);
+static void standardTiming(unsigned char *data); 
+static void predefinedSettings(unsigned char Tim, Predefined_DDC *array,
+								 int start, int count);
+static int checkHeader(void); 
+static void add2List(unsigned long xres,unsigned long yres,unsigned long hz);
+static void sortList(void);
+static void dumpList(void);
+
+static unsigned long Current;
+static unsigned long SupportedModes[MAX_MODES];
+static unsigned long TempModes[MAX_MODES];
+static unsigned long temp;
+static Platform_DDC_ops *ddc_ops=0x0;
+
+/* functions to support the ddc protocols are included in this file struct.*/
+#ifdef PLATFORM_5530
+#include "ddc_5530.c"
+
+Platform_DDC_ops ddc_5530={
+	init_5530,
+	ReadByte_5530,
+	StartBit_5530,
+	StopBit_5530,
+	Ack_5530,
+	waitForAck_5530,
+	requestData_5530,
+	startXfer_5530,
+	endXfer_5530,
+	SetSCL_5530,
+	ClearSCL_5530,
+	ClearSDA_5530,
+	SetSDA_5530,
+	GetSDA_5530,
+	GetSCL_5530
+};
+#endif
+
+#ifdef PLATFORM_x200
+#include "ddc_x200.c"
+Platform_DDC_ops ddc_x200={
+	init_x200,
+	ReadByte_x200,
+	StartBit_x200,
+	StopBit_x200,
+	Ack_x200,
+	waitForAck_x200,
+	requestData_x200,
+	startXfer_x200,
+	endXfer_x200,
+	SetSCL_x200,
+	ClearSCL_x200,
+	ClearSDA_x200,
+	SetSDA_x200,
+	GetSDA_x200,
+	GetSCL_x200
+};
+#endif
+
+/*----------------------------------------------------------------------------
+ * SortList.
+ *
+ * Description	  : This function used for sorting out modes in order
+ *
+ * Parameters     : None
+ *
+ * Returns		  : None
+ *
+ * Comments       : This is keep the supported modes by the hw in order.
+*----------------------------------------------------------------------------
+*/
+void sortList()
+{
+	int i,j;
+	int length;
+	length = MAX_MODES - 1;	
+
+	for(i=0;i<MAX_MODES;i++)
+	{
+		for (j=0;j<length;j++)
+		{
+			if(SupportedModes[j] > SupportedModes[j+1])
+			{
+				temp = SupportedModes[j+1];
+				SupportedModes[j+1] = SupportedModes[j];
+				SupportedModes[j] = temp;
+			}
+		}
+		length--;
+	}
+      /*Now put it it descending order */
+	for(i=0;i<MAX_MODES;i++)
+	{
+		TempModes[i] = SupportedModes[MAX_MODES - 1 - i];
+	}
+      /* Now put the TempModes in same order back into SupportedModes */
+	for(i=0;i<MAX_MODES;i++)
+	{
+		SupportedModes[i] = TempModes[i];
+	}
+}
+
+/*----------------------------------------------------------------------------
+ * add2List.
+ *
+ * Description		: This fuction will add the mode data into the prepared list.
+ *                    next at the end. 	
+ * Parameters       :
+ *
+ *     xres         : Specifies the horz resolution.
+ *     yres         : Specifies the  vert resolution.
+ *      hz          : Specfies the mode timing.
+ *
+ * Returns			: None.
+ *
+ * Comments         : This is used to navigate the list and sets the desird
+ *                    mode.
+ *----------------------------------------------------------------------------
+*/
+
+void add2List(unsigned long xres, unsigned long yres, unsigned long hz)
+{
+	RETAILMSG( 0,(_T("%d %d %d = "), xres, yres, hz));
+	SupportedModes[Current] = (xres << 20) | (yres << 8) | (hz & 0xff);
+	RETAILMSG( 0,(_T("%x\n"), SupportedModes[Current]));
+	Current ++;
+}
+
+/*----------------------------------------------------------------------------
+ * nextFromList.
+ *
+ * Description		: This fuction will check read  the mode list and points to
+ *                    next in the list. 	
+ * Parameters       :
+ *	 xres			: Specifies the horz resolution.
+ *     yres         : Specifies the  vert resolution.
+ *      hz          : Specfies the mode timing.
+ *
+ * Returns			: None.
+ *
+ * Comments         : This is used to navigate the list and sets the desired
+ *                    mode.
+ *----------------------------------------------------------------------------
+*/
+void nextFromList(unsigned long *xres, unsigned long *yres, unsigned long *hz)
+{
+	*hz = SupportedModes[Current]  & 0xff;
+	*yres = (SupportedModes[Current]  >> 8) & 0xfff;
+	*xres = (SupportedModes[Current]  >> 20) & 0xfff;
+	Current ++;
+}
+
+/*----------------------------------------------------------------------------
+ * dumpList.
+ *
+ * Description	  : This function to prepare supported mode list.
+	
+ * Parameters     : None
+ *
+ * Returns		  : None.
+ *
+ * Comments       : This may be called to check the list of modes supported.
+ *
+ *----------------------------------------------------------------------------
+*/
+
+void dumpList() 
+{
+	int unsigned long i;
+	for(i=0; i< Current; i++) {
+		RETAILMSG( 0,(_T("%d %d %d\n"),
+			(SupportedModes[i]  >> 20) & 0xfff,
+			(SupportedModes[i]  >> 8) & 0xfff,
+			SupportedModes[i]  & 0xff));
+	}
+}
+
+
+/*----------------------------------------------------------------------------
+ * PredefiedSettings.
+ *
+ * Description		: This function is to get the VESA estimated manual timing
+                      based on manfacturer's list.
+ * Parameters       :
+ *     Tim          : Specifies the timing data from header read from hw.
+ *     array        : Specifies the data of std mfgtiming.
+ *     Start        : Specfies the index.* not used here?.
+ *     count        : Specifies the no of mode count.
+ * Returns			: None
+ *
+ * Comments         : List is prapared based on VESA timings.
+ *
+ *----------------------------------------------------------------------------
+*/
+void predefinedSettings(unsigned char Tim, Predefined_DDC *array,
+								 int start, int count) 
+{ 
+        int i;
+	for (i = 0; i < count; i++) {
+		if(Tim & ((unsigned char)(0x1 << i)))
+			add2List(array[i].xres, array[i].yres, array[i].hz);
+	}
+}
+/*----------------------------------------------------------------------------
+ * standardTiming.
+ *
+ * Description		: This function is to make standard timing list with VESA
+					  standard timings.
+ * Parameters       :
+ *       data       : Pointer has mode data.
+ * Returns			: None.
+ *
+ * Comments         : None.
+ *
+ *----------------------------------------------------------------------------
+*/
+void standardTiming(unsigned char *data) 
+{
+	unsigned long width, height;
+	unsigned long freq, ratio, pos;
+	int i;
+	for (i = 0; i < 8; i++) {
+		/* value = (HorizTiming /8) - 31 */
+		pos = VESA1_EST_STAND_TIM + (i <<1); /* Each timing uses 2 Bytes as info. */
+		if((data[pos] <= 0x1 ) && (data[pos + 1] <= 0x1))
+			continue;
+		width = (data[pos] + 31) << 3;
+		freq = 60+(data[pos + 1] & 0x3F);
+		ratio = (data[pos + 1] & 0xC0) >> 6;
+		height = (width / asp[ratio].xRatio) * asp[ratio].yRatio;
+
+		add2List(width, height, freq);
+		
+	RETAILMSG( 0,(_T("%d(%d %d) = %3dX%3d %dHz\n"),i, data[pos], data[pos+1], width, height, freq));
+	}
+}
+
+/*----------------------------------------------------------------------------
+ * CheckHeader.
+ *
+ * Description		:	This function checks the read ddc header with std EDID
+ *						header.
+ * Parameters		:	None
+ *
+ * Returns			:	returns TRUE if both headers are equal.
+ *
+ * Comments         :	This is to check the read header data.
+ *
+ *----------------------------------------------------------------------------
+*/
+
+int checkHeader()
+{
+	int i;
+	for (i = 0; i < 8; i++) {
+		if(displayData[i] != EDID_Header[i])
+			return 0;
+	}
+	return 1;
+}
+
+/*----------------------------------------------------------------------------
+ * DumpData.
+ *
+ * Description		: This function looks like redundant
+ *
+ * Parameters		: None
+ *
+ * Returns			:
+ *
+ * Comments			: None
+ *
+ *----------------------------------------------------------------------------
+*/
+static void dumpData(unsigned char *data, int length)
+{
+	int i;
+	for (i = 0; i < length; i++) {
+		RETAILMSG( 0,(_T("%d = %2X %3d\n"),i, data[i],data[i]));
+	}
+}
+
+/*----------------------------------------------------------------------------
+ * ddc_init.
+ *
+ * Description	  : This function detects the type of video HW and gets ddc data
+ *
+ *
+ * Parameters     : None
+ *
+ * Returns		  : None
+ *
+ * Comments       : This readsthe header and sort list of modes.
+ *
+ *----------------------------------------------------------------------------
+*/
+
+void ddc_init() 
+{
+	unsigned long video_hw = gfx_detect_video();
+
+#ifdef PLATFORM_5530
+	if (video_hw == GFX_VID_CS5530)
+		ddc_ops = &ddc_5530;
+#endif
+
+#ifdef PLATFORM_x200
+	if ((video_hw == GFX_VID_SC1200) && Get_9211_Details())
+		ddc_ops = &ddc_x200;
+#endif
+
+	displaySupports = 0;
+	memset(displayData, 0x0, DisplayDataLength);
+	memset(SupportedModes, 0x0, sizeof(unsigned long) * MAX_MODES);
+	Current = 0;
+
+	if(ddc_ops == 0x0) /* none mapped, ERROR */
+		return;
+
+	ddc_ops->startXfer();
+	ddc_ops->init();
+	getBlock(displayData, DisplayDataLength);
+	ddc_ops->endXfer();
+	dumpData(displayData, DisplayDataLength);
+    if(checkHeader()) 
+	{
+		standardTiming(displayData);
+		predefinedSettings(displayData[VESA1_EST_MANU_TIM], MfgTim2, 7, 1);
+		predefinedSettings(displayData[VESA1_EST_TIM2], EstTim2, 0, 8);
+		predefinedSettings(displayData[VESA1_EST_TIM1], EstTim1, 0, 8);
+		dumpList();
+		sortList();
+		dumpList();
+	Current = 0;
+	}
+}
+
+/*----------------------------------------------------------------------------
+ * ddc_Cleanup.
+ *
+ * Description	  : This function will bw called at the end of ddc.
+ *
+ *
+ * Parameters     : None
+ *
+ * Returns		  : None
+ *
+ * Comments       : it may be enhanced.
+ *
+ *----------------------------------------------------------------------------
+*/
+
+void ddc_cleanup()
+{
+	RETAILMSG( 0,(TEXT("DDC1_2B::~DDC1_2B\n")));
+}
+
+
+/* Wait for microSeconds */
+void wait(int uSec) 
+{
+	gfx_delay_milliseconds(uSec);
+}
+
+/*----------------------------------------------------------------------------
+ * getBlock.
+ *
+ * Description		: This function reads the ddc data
+ *
+ *
+ * Parameters       :
+ *      block       : data will be stored in this ponter
+ *      length      : Specifies the length of data to be read.
+ * Returns			: None
+ *
+ * Comments         : Block of data will be read by readbyte,readbit routines.
+ *
+ *----------------------------------------------------------------------------
+*/
+void getBlock(unsigned char *block, int length) 
+{
+
+	int cksum = 0;
+	int i, end = length - 1;
+
+	RETAILMSG( 0,(TEXT("getBlock\n")));
+	ddc_ops->requestData();
+
+	for (i = 0; i < length; i++) {
+		block[i] = ddc_ops->ReadByte((i != end));
+		cksum += (int)block[i];
+	}
+	ddc_ops->StopBit();
+
+	RETAILMSG( 0,(TEXT("getBlock %d\n"),cksum));
+
+	if ((cksum & 0xff) != 0) {
+		RETAILMSG( 1,(TEXT("Checksum Error\n")));
+	}
+}
+
+/*----------------------------------------------------------------------------
+ * ReadBit.
+ *
+ * Description	  : This function read the DDC data by one bit
+ *
+ *
+ * Parameters     : None
+ * Returns		  : One bit information by a flag.
+ *
+ * Comments       : Date will be read by  a bit.
+ *
+*----------------------------------------------------------------------------
+*/
+
+int ReadBit()
+{
+	RETAILMSG( 0,(TEXT("getBit\n")));
+	wait(DEFAULTDELAY);
+	ddc_ops->ClearSCL();
+	wait(DEFAULTDELAY);
+	WaitSCLHigh();
+	wait(DEFAULTDELAY);
+	return ddc_ops->GetSDA();
+}
+
+/*----------------------------------------------------------------------------
+ * WaitSCLHigh.
+ *
+ * Description		: This function provides the conditional delay till SCL clock
+ *                    goes high.
+ *
+ * Parameters       :
+ *       data       : None.
+ * Returns			: None
+ *
+ * Comments         : Date will be send by bit by bit.
+ *
+*----------------------------------------------------------------------------
+*/
+void WaitSCLHigh()
+{
+	unsigned long target=0;
+
+	RETAILMSG( 0,(TEXT("WaitSCLHigh\n")));
+	ddc_ops->SetSCL();
+	/* slow down trasfer  */
+#ifndef _WIN32_WCE
+	/* introduce delay for SetSCL to work. This is not required in the
+	* else part, since GetTickCount() function call adds the delay 
+	*/
+	wait(DEFAULTDELAY); 
+
+	for (;;) {
+		if (ddc_ops->GetSCL() == 1) {
+			break;
+		} 
+          /* else if (GetTickCount() > target) {
+			RETAILMSG( 1,(TEXT("timeout")));
+		}*/
+		RETAILMSG( 0,(TEXT("WaitSCLHigh - Delay 2 u Sec\n")));
+	}
+#else
+	target = GetTickCount() + 2;
+
+	for (;;) {
+		if (ddc_ops->GetSCL() == 1) {
+			break;
+		} else if (GetTickCount() > target) {
+			RETAILMSG( 1,(TEXT("timeout")));
+			return;
+		}
+		RETAILMSG( 0,(TEXT("WaitSCLHigh - Delay 2 u Sec\n")));
+	}
+#endif
+}
+
+/*----------------------------------------------------------------------------
+ * SendByte.
+ *
+ * Description		: This function is send one byte of data
+ *
+ *
+ * Parameters       :
+ *       data       : Specifies the data to be send.
+ * Returns			: None
+ *
+ * Comments         : Date will be send by bit by bit.
+ *
+*----------------------------------------------------------------------------
+*/
+void SendByte(unsigned char data) 
+{
+	int i;
+	RETAILMSG( 0,(TEXT("sendByte Enter\n")));
+	for (i = 7; i >= 0; i--) {
+		SendBit((data >> i) & 1);
+	}
+
+	if (! ddc_ops->waitForAck()) {
+		RETAILMSG( 1,(TEXT("NACK received\n")));
+	}
+	ddc_ops->ClearSCL();
+	RETAILMSG( 0,(TEXT("sendByte Exit\n")));
+}
+
+
+/*----------------------------------------------------------------------------
+ * SendBit.
+ *
+ * Description		: This function is send one bit
+ *
+ *
+ * Parameters       :
+ *       flag       : Specifies masked data bit by a flag High or Low.
+ * Returns			: None
+ *
+ * Comments         : None.
+ *
+*----------------------------------------------------------------------------
+*/
+void SendBit(int flag) 
+{
+	RETAILMSG( 0,(TEXT("sendBit\n")));
+	wait(DEFAULTDELAY);
+	ddc_ops->ClearSCL();
+	wait(DEFAULTDELAY);
+	if (flag) {
+		ddc_ops->SetSDA();
+	} else {
+		ddc_ops->ClearSDA();
+	}
+	wait(DEFAULTDELAY);
+	WaitSCLHigh();
+}
+
diff -uNr linux-2.4.31/drivers/video/nsc/ddc/ddc_x200.c linux-fb/drivers/video/nsc/ddc/ddc_x200.c
--- linux-2.4.31/drivers/video/nsc/ddc/ddc_x200.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/ddc/ddc_x200.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,613 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * File Contents: This file contains the function definitions to access the  
+ *                hardware x200   I/O compaion.
+ *
+ * SubModule:     Display Data Channel support.
+ * </DOC_AMD_STD>
+ */
+
+#include "ddc_x200.h"
+
+/* Glen Han 01/25/2001, modified code to support DORADO board
+ *DDC DORADO implementation with GPIO pins
+ *SCL is gpio 7, SDA is gpio 18, CSDDC is gpio 9
+ */
+#define SCx2xx_GPIO_BASE 0x6400
+#define SCx2xx_GPDO0 0x0000
+#define SCx2xx_GPDI0 0x0004
+#define SCx2xx_GPPIN_SEL 0x0020
+#define SCx2xx_GPPIN_CFG 0x0024
+#define GPOUT (SCx2xx_GPIO_BASE + SCx2xx_GPDO0) 
+#define GPIN (SCx2xx_GPIO_BASE + SCx2xx_GPDI0) 
+#define GPSEL (SCx2xx_GPIO_BASE + SCx2xx_GPPIN_SEL) 
+#define GPCFG (SCx2xx_GPIO_BASE + SCx2xx_GPPIN_CFG)
+#define OUTPUT_ENABLE 0x00000003 
+#define INPUT_ENABLE 0x00000000 
+#define CLOCK_PIN_MASK 0x00000080
+#define DATA_PIN_MASK 0x00040000
+#define CSDDC_PIN_MASK 0x00000200
+#define CLOCK_PIN_SEL 0x00000007
+#define DATA_PIN_SEL 0x00000012
+#define CSDDC_PIN_SEL 0x00000009
+
+int Get_9211_Details()
+{
+	unsigned long pmr;
+	
+#define SC_CB_ADDR      0x9000
+#define SC_PMR          0x30
+#define SC_PMR_TFTIDE   0x01000000
+#define SC_PMR_TFTPP    0x00800000
+#define SC_PMR_ETFT     0x00000400
+
+	pmr = gfx_ind(SC_CB_ADDR + SC_PMR);
+	RETAILMSG( 1,(TEXT("Get_9211_Details %X\n"),pmr));
+
+	if (!(pmr & SC_PMR_TFTIDE)) {
+		// The SC_PMR_TFTIDE bit is off, go check if the TFT is 
+		// multiplexed with the parallel port.
+		if (pmr & SC_PMR_TFTPP) {
+			pmr |= SC_PMR_ETFT;     // Make sure this is on.
+			gfx_outd(SC_CB_ADDR + SC_PMR, pmr);
+		} else {
+			// Failed.  The hardware configuration precludes a TFT.
+			return(0); 
+		}
+	}
+	return(1); 
+}
+
+/*----------------------------------------------------------------------------
+ * init_x200.
+ *
+ * Description	  : This function is called to configure the  Serial Data
+ *					line to probe the monitor.
+ *
+ * Parameters     : None
+ *
+ * Returns		  : None
+ *
+ * Comments       : This function  should be invoked before readbyte or write
+ *                   byte routines.
+*----------------------------------------------------------------------------
+*/
+void init_x200() 
+{
+	RETAILMSG( 0,(TEXT("SCx200 setup\n")));
+	requestData_x200();
+	ReadByte_x200(0);
+	StopBit_x200();
+}
+/*----------------------------------------------------------------------------
+ * ReadByte_x200.
+ *
+ * Description	  : This function reads the data bit by bit and setting ack
+ *                    after the one byte read.
+ *
+ * Parameters       
+ *       ack      : Gets the one byte data.
+ * Returns		  : Returning one byte information after read bit.
+ *
+ * Comments       : This function  should be invoked before readbyte or write
+ *                : byte routines.
+*----------------------------------------------------------------------------
+*/
+
+unsigned char ReadByte_x200(int ack)
+{
+	unsigned char val = 0;
+	int i;
+	RETAILMSG( 0,(TEXT("getByte\n")));
+	ConfigSDAin_x200();
+	for (i = 0; i < 8; i++) {
+		val <<= 1;
+		val |= ReadBit();
+	}
+
+	Ack_x200(ack);
+	return val;
+}
+/*---------------------------------------------------------------------------
+ * StartBit_x200.
+ *
+ * Description	  : This function sending out the start bit of serial data
+ *
+ *
+ * Parameters     : None
+ *
+ * Returns		  : None
+ *
+ * Comments       : This function indicates the begining ddc seiral data.
+ *
+*----------------------------------------------------------------------------
+*/
+void StartBit_x200()
+{
+	RETAILMSG( 0,(TEXT("startBit\n")));
+	wait(DEFAULTDELAY);
+	ClearSCL_x200();
+	wait(DEFAULTDELAY);
+	SetSDA_x200();
+	ConfigSDAout_x200();
+	wait(DEFAULTDELAY);
+	WaitSCLHigh();
+	wait(DEFAULTDELAY);
+	ClearSDA_x200();
+	wait(DEFAULTDELAY);
+}
+
+/*---------------------------------------------------------------------------
+ * StopBit_x200.
+ *
+ * Description	  : This function sending out the stop bit of serial data
+ *
+ *
+ * Parameters     : None
+ *
+ * Returns		  : None
+ *
+ * Comments       : This function indicates the end ddc seiral data.
+ *
+*----------------------------------------------------------------------------
+*/
+void StopBit_x200() 
+{
+	RETAILMSG( 0,(TEXT("stopBit\n")));	
+	/* always follow master ack, already in SDA out mode */
+	wait(DEFAULTDELAY);
+	ClearSCL_x200();
+	wait(DEFAULTDELAY);
+	ClearSDA_x200();
+	wait(DEFAULTDELAY);
+	WaitSCLHigh();
+	wait(DEFAULTDELAY);
+	SetSDA_x200();
+	wait(2);
+}
+
+/*---------------------------------------------------------------------------
+ * Ack_x200.
+ *
+ * Description	  : This sends out the ack data
+ *
+ * Parameters       
+ *        flag    : Value read in ReaByte routine is passed
+ * Returns		  : None
+ *
+ * Comments       : None
+*----------------------------------------------------------------------------
+*/
+void Ack_x200(int flag)
+{
+	RETAILMSG( 0,(TEXT("ACK\n")));
+	wait(DEFAULTDELAY);
+	ClearSCL_x200();
+	wait(DEFAULTDELAY);
+	if (flag) {
+		ClearSDA_x200();
+	} else {
+		SetSDA_x200();
+	}
+	ConfigSDAout_x200();
+	WaitSCLHigh();
+	wait(10);		/* let transmitter has time to sense it */
+	ClearSCL_x200();
+	wait(DEFAULTDELAY);
+	SetSDA_x200();	       /* is it real necessary? */
+	RETAILMSG( 0,(TEXT("ACK Exit\n")));
+}
+
+/*---------------------------------------------------------------------------
+ * waitForAck:
+ *
+ * Description	  : This routine waits the ack SDL data.
+ *
+ * Parameters     : none
+ *
+ * Returns		  : None
+ *
+ * Comments       : None
+*----------------------------------------------------------------------------
+*/
+int waitForAck_x200()
+{
+	unsigned long target;
+	int	i = 0;
+
+	RETAILMSG( 0,(TEXT("waitForACK\n")));
+	wait(DEFAULTDELAY);
+	ClearSCL_x200();
+	wait(DEFAULTDELAY);
+	SetSDA_x200();
+	ConfigSDAin_x200();
+	WaitSCLHigh();
+	wait(5);
+
+#ifndef _WIN32_WCE
+	/* Try for two times (2 uSec) */
+	for (i=0; i<2; i++) {
+		wait(DEFAULTDELAY);
+		if (GetSDA_x200() == 0) {
+		return 1;
+		} 
+	}
+	/* time out */
+	return 0;
+
+#else
+	target = GetTickCount() + 2;
+	for (;;) {
+		wait(DEFAULTDELAY);
+		if (GetSDA_x200() == 0) {
+			return 1;
+		} else if(GetTickCount() > target) {
+			return 0;
+		}
+	}
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * requestData.
+ *
+ * Description	  : This routine request the data and configure SDA to Rx mode.
+ *
+ * Parameters     : none
+ *
+ * Returns		  : None
+ *
+ * Comments       : None
+*----------------------------------------------------------------------------
+*/
+
+void requestData_x200() 
+{
+	RETAILMSG( 0,(TEXT("requestData\n")));
+	StartBit_x200();
+	SendByte(0xa0);
+	ConfigSDAout_x200();
+	SendByte(0);
+
+	StartBit_x200();
+	SendByte(0xa1);
+}
+
+
+/*---------------------------------------------------------------------------
+ * startXfer_x200.
+ *
+ * Description	  : This routine is called to sets SDA and SCL outto high state
+	                when the transfer starts.
+ * To start DDC transfer
+ * 1. Enable DDC access by making chip control pin active low
+ * 2. Configuer SCL and SDA as output pins 
+ * 3. Issue an stop condition to clean up any possible slave device mess  
+ *   caused by other application.
+ *. Toggle clock several times to let slave device finish 
+ *  internal housekeeping job
+* Parameters     : None
+ * Returns		  : None
+ *
+ * Comments       : SCL should be high when toggling.
+*----------------------------------------------------------------------------
+*/
+
+void startXfer_x200() 
+{
+	int i;
+	RETAILMSG( 0,(TEXT("startXfer\n")));
+	ClearCSDDC_x200();
+	wait(10);
+	ConfigSCLout_x200();
+	ConfigSDAout_x200();
+	StopBit_x200();
+	wait(10);
+	for (i = 0; i < 10; i++)
+	{
+		ClearSCL_x200();
+		wait(DEFAULTDELAY);
+		SetSCL_x200();
+		wait(DEFAULTDELAY);
+	}
+}
+
+/*---------------------------------------------------------------------------
+ * endXfer_x200.
+ *
+ * Description		: This routine is called to sets SDA to low state when the
+ *                    transfer ends.
+ *
+ * Parameters		: None
+ * Returns			: None
+ *
+ * Comments         : SCL should be high when toggling.
+*----------------------------------------------------------------------------
+*/
+void endXfer_x200() 
+{
+	int i;
+	wait(DEFAULTDELAY);
+	for (i = 0; i < 10; i++)
+	{
+		ClearSCL_x200();
+		wait(DEFAULTDELAY);
+		SetSCL_x200();
+		wait(DEFAULTDELAY);
+	}
+	ConfigSDAin_x200();				/* tristate pin */
+	ConfigSCLin_x200();				/* tristate pin */
+	RETAILMSG( 0,(TEXT("endXfer\n")));	
+	wait(10);
+}
+
+
+/***************************************************************
+*  H/W DEPENDENT LOW LAYER ROUTINES
+****************************************************************/
+
+/*---------------------------------------------------------------------------
+ * SetCSDDC_x200.
+ *
+ * Description	  : This routine disable DDC acesss and enable cs9211 serial
+	                access.
+ *Set CSDDC chip select control pin high to disable DDC access 
+ * and enable cs9211 serial access
+ * Parameters     : None
+ * Returns		  : None
+ *
+ * Comments       : None.
+*----------------------------------------------------------------------------
+*/
+void SetCSDDC_x200()
+{
+	unsigned long data = gfx_ind(GPIN);
+	data |= CSDDC_PIN_MASK;
+	RETAILMSG( 0,(TEXT("Set CSDDC to disable DDC access \n")));
+	gfx_outd(GPOUT, data);
+	wait(10); /*10 */
+}
+
+/*---------------------------------------------------------------------------
+ * ClearCSDDC_x200.
+ *
+ * Description	  : This routine enable DDC acesss and disble cs9211 serial
+	                access.
+ * Set CSDDC chip select control pin low to enable DDC access 
+ *and disable cs9211 serial access
+ * Parameters     : None
+ * Returns		  : None
+ *
+ * Comments       : None.
+*----------------------------------------------------------------------------
+*/
+void ClearCSDDC_x200()
+{
+	unsigned long data = gfx_ind(GPIN);
+	data &= ~CSDDC_PIN_MASK;
+	RETAILMSG( 0,(TEXT("Clear CSDDC to enable DDC access %X\n"),data));
+	gfx_outd(GPOUT, data);
+	wait(10); /* 10 */
+}
+
+/*---------------------------------------------------------------------------
+ * SetSCL_x200.
+ *
+ * Description	  : This routine sets the serial clock line to high.
+ *
+ *
+ * Parameters     : None
+ * Returns		  : None
+ *
+ * Comments       : none
+*----------------------------------------------------------------------------
+*/
+void SetSCL_x200() 
+{
+	unsigned long data = gfx_ind(GPIN);
+	data |= CLOCK_PIN_MASK;
+	RETAILMSG( 0,(TEXT("SetSCL\n")));
+	gfx_outd(GPOUT, data);
+}
+
+
+/*---------------------------------------------------------------------------
+ * ClearSCL_x200.
+ *
+ * Description	  : This routine sets the serial clock line to low.
+ *
+ *
+ * Parameters     : None
+ * Returns		  : None
+ *
+ * Comments       : none
+*----------------------------------------------------------------------------
+*/
+void ClearSCL_x200() 
+{
+	unsigned long data = gfx_ind(GPIN);
+	data &= ~CLOCK_PIN_MASK;
+	RETAILMSG( 0,(TEXT("DDCclockLo %X\n"),data));
+	gfx_outd(GPOUT, data);
+}
+/*---------------------------------------------------------------------------
+ * GetSCL_x200.
+ *
+ * Description	  : This routine gets the of SCL data .
+ *
+ *
+ * Parameters     : None
+ * Returns		  : returns SCL data.
+ *
+ * Comments       : none
+*----------------------------------------------------------------------------
+*/
+int GetSCL_x200() 
+{
+	unsigned long data = gfx_ind(GPIN);
+	RETAILMSG( 0,(TEXT("GetSCL %X\n"), data));
+	data &= CLOCK_PIN_MASK;
+	return (data >> CLOCK_PIN_SEL);
+}
+
+
+/*---------------------------------------------------------------------------
+ * SetSDA_x200.
+ *
+ * Description	  : This routine sets the serial data line to high.
+ *
+ *
+ * Parameters     : None
+ * Returns		  : None
+ *
+ * Comments       : none
+*----------------------------------------------------------------------------
+*/
+void SetSDA_x200() 
+{
+	unsigned long data = gfx_ind(GPIN);
+	data |= DATA_PIN_MASK;
+	RETAILMSG( 0,(TEXT("SetSDA %X\n"), data));
+	gfx_outd(GPOUT, data);
+}
+
+/*---------------------------------------------------------------------------
+ * ClearSDA_x200.
+ *
+ * Description	  : This routine sets the serial data line to low.
+ *
+ *
+ * Parameters     : None
+ * Returns		  : None
+ *
+ * Comments       : none
+*----------------------------------------------------------------------------
+*/
+void ClearSDA_x200() 
+{
+	unsigned long data = gfx_ind(GPIN);
+	data &= ~DATA_PIN_MASK;
+	RETAILMSG( 0,(TEXT("ClearSDA %X\n"), data));
+	gfx_outd(GPOUT, data);
+}
+
+/*---------------------------------------------------------------------------
+ * GetSDA_x200.
+ *
+ * Description	  : This routine gets the of SDL data .
+ *
+ *
+ * Parameters     : None
+ * Returns		  : returns SCL data.
+ *
+ * Comments       : None
+*----------------------------------------------------------------------------
+*/
+int GetSDA_x200() 
+{
+	unsigned long data = gfx_ind(GPIN);
+	RETAILMSG( 0,(TEXT("GetSDA 0x%8X\n"), data));
+	data &= DATA_PIN_MASK;
+	return (data >> DATA_PIN_SEL);
+}
+
+/*---------------------------------------------------------------------------
+ * ConfigSDAout_x200.
+ *
+ * Description	  : This routiine selects GPIO base and sets SDA pin for out.
+ *
+ *
+ * Parameters     : None
+ * Returns		  : None.
+ *
+ * Comments       : None
+*----------------------------------------------------------------------------
+*/
+
+void ConfigSDAout_x200() 
+{
+ 	gfx_outd(GPSEL, DATA_PIN_SEL);
+ 	gfx_outd(GPCFG, OUTPUT_ENABLE);
+	wait(5); //10
+}
+/*---------------------------------------------------------------------------
+ * ConfigSDAin_x200.
+ *
+ * Description	  : This routiine selects GPIO base and sets SDA pin for in.
+ *
+ *
+ * Parameters     : None
+ * Returns		  : None.
+ *
+ * Comments       : None
+*----------------------------------------------------------------------------
+*/
+void ConfigSDAin_x200() 
+{
+ 	gfx_outd(GPSEL, DATA_PIN_SEL);
+ 	gfx_outd(GPCFG, INPUT_ENABLE);
+	wait(5); /* 10 */
+}
+/*---------------------------------------------------------------------------
+ * ConfigSCLout_x200.
+ *
+ * Description	  : This routiine selects GPIO base and sets SCL pin for in.
+ *
+ *
+ * Parameters     : None
+ * Returns		  : None.
+ *
+ * Comments       : None
+*----------------------------------------------------------------------------
+*/
+
+
+
+void ConfigSCLout_x200() 
+{
+	ClearSCL_x200();	/* don't disturb any device */
+ 	gfx_outd(GPSEL, CLOCK_PIN_SEL);
+ 	gfx_outd(GPCFG, OUTPUT_ENABLE);
+	wait(5); //10
+}
+
+/*---------------------------------------------------------------------------
+ * ConfigSCLin_x200.
+ *
+ * Description	  : This routiine selects GPIO base and sets SCL pin for in.
+ *
+ *
+ * Parameters     : None
+ * Returns		  : None.
+ *
+ * Comments       : None
+*----------------------------------------------------------------------------
+*/
+void ConfigSCLin_x200() 
+{
+ 	gfx_outd(GPSEL, CLOCK_PIN_SEL);
+ 	gfx_outd(GPCFG, INPUT_ENABLE);
+	wait(5); /* 10 */
+}
diff -uNr linux-2.4.31/drivers/video/nsc/ddc/ddc_x200.h linux-fb/drivers/video/nsc/ddc/ddc_x200.h
--- linux-2.4.31/drivers/video/nsc/ddc/ddc_x200.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/ddc/ddc_x200.h	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,57 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * File Contents: This file contains the function prototypes to access the  
+ *                hardware x200 I/O compaion.
+ *
+ * SubModule:     Display Data Channel support.
+ * </DOC_AMD_STD>
+ */
+
+#ifndef _ddc_x200_h
+#define _ddc_x200_h
+
+void init_x200(void);
+int waitForAck_x200(void);
+void SetCSDDC_x200(void);
+void ClearCSDDC_x200(void);
+void SetSCL_x200(void);
+void ClearSCL_x200(void);
+int GetSCL_x200(void);
+void SetSDA_x200(void);
+void ClearSDA_x200(void);
+int GetSDA_x200(void);
+void ConfigSDAout_x200(void); 
+void ConfigSDAin_x200(void);
+void ConfigSCLout_x200(void); 
+void ConfigSCLin_x200(void);
+void startXfer_x200(void);
+void endXfer_x200(void);
+void requestData_x200(void);
+unsigned char ReadByte_x200(int);
+void StartBit_x200(void);
+void StopBit_x200(void);
+void Ack_x200(int);
+
+#endif /* __ddc_x200_h */
diff -uNr linux-2.4.31/drivers/video/nsc/ddc/readme.txt linux-fb/drivers/video/nsc/ddc/readme.txt
--- linux-2.4.31/drivers/video/nsc/ddc/readme.txt	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/ddc/readme.txt	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,121 @@
+DDC Library
+Release 1.1.1
+OS - Can be used in all OS's.
+Feb 28, 2003
+Developer -  Sarma Kolluru
+
+-----------------------------------------------------------------------------
+PRODUCT INFORMATION
+-----------------------------------------------------------------------------
+DDC library is set of functions enabling the driver to give DDC support.
+The DDC library is supported on Centaurus and Dorado.
+The DDC library can detect the resolutions supported by the monitor 
+connected to the VGA connector. 
+ 
+   \readme.txt        This file 
+
+-----------------------------------------------------------------------------
+BUILD INSTRUCTIONS					
+----------------------------------------------------------------------------- 
+The DDC subdirectory needs to be copied in the driver directory. 
+-  Run "/root/crlf/crlf -a" in Linux OS.
+-----------------------------------------------------------------------------
+INSTALLATION INSTRUCTIONS	
+----------------------------------------------------------------------------- 
+There is no instalation and to be treaded as a driver source code extension.
+-----------------------------------------------------------------------------
+UNIT TEST
+DDC library when compiled is a part of the driver and cannot be unit tested.
+-----------------------------------------------------------------------------
+
+-----------------------------------------------------------------------------
+REVISION HISTORY
+-----------------------------------------------------------------------------
+Version changes	v1.1.1  02/28/03    
+-----------------------------------------------------------------------------
+Dependencies:
+	- crlf v1.0.1
+
+-----------------------------------------------------------------------------
+FUNCTIONAL CHANGES
+-----------------------------------------------------------------------------
+Added National Copyright header which replaced the GPL and BSD..
+-----------------------------------------------------------------------------
+DEFECTS CORRECTED
+-----------------------------------------------------------------------------
+- None listed
+-----------------------------------------------------------------------------
+FILE CHANGES
+	ddc_init.c
+	ddc_defs.h
+	ddc_x200.c
+	ddc_x200.h
+	ddc_5530.c
+	ddc_5530.h
+	ddc.c
+	ddc.h
+-----------------------------------------------------------------------------
+Version changes	v1.1.0  01/23/03    
+-----------------------------------------------------------------------------
+Dependencies:
+	- crlf v1.0.1
+
+-----------------------------------------------------------------------------
+FUNCTIONAL CHANGES
+-----------------------------------------------------------------------------
+On SCx200 based platforms the DDC support is provided through 9211. 
+If we can't find 9211 support then we have to return with error. 
+This can be seen on Krill platform.
+-----------------------------------------------------------------------------
+DEFECTS CORRECTED
+-----------------------------------------------------------------------------
+- None listed
+-----------------------------------------------------------------------------
+FILE CHANGES
+	ddc_init.c
+	ddc_x200.c
+-----------------------------------------------------------------------------
+Version changes	v1.0.3  06/06/01    
+-----------------------------------------------------------------------------
+Dependencies:
+	- crlf v1.0.1
+	- Durango 2.31.00
+
+-----------------------------------------------------------------------------
+FUNCTIONAL CHANGES
+-----------------------------------------------------------------------------
+Function's w/o parameters should have void.
+-----------------------------------------------------------------------------
+DEFECTS CORRECTED
+-----------------------------------------------------------------------------
+- None listed
+-----------------------------------------------------------------------------
+FILE CHANGES
+	ddc_init.c
+	ddc_defs.h
+	ddc_x200.c
+	ddc_x200.h
+	ddc_5530.h
+	ddc.h
+-----------------------------------------------------------------------------
+Version changes	v1.0.2  04/26/01    
+-----------------------------------------------------------------------------
+Dependencies:
+	- Durango 2.29.00
+
+-----------------------------------------------------------------------------
+FUNCTIONAL CHANGES
+-----------------------------------------------------------------------------
+Got rid of WINNT defines and NT code. The code is made generalised and 
+ifdef only for WINCE.
+
+-----------------------------------------------------------------------------
+DEFECTS CORRECTED
+-----------------------------------------------------------------------------
+- None listed
+-----------------------------------------------------------------------------
+FILE CHANGES
+	ddc_5530.c
+	ddc_x200.c
+	ddc_init.c
+-----------------------------------------------------------------------------
diff -uNr linux-2.4.31/drivers/video/nsc/ddc.c linux-fb/drivers/video/nsc/ddc.c
--- linux-2.4.31/drivers/video/nsc/ddc.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/ddc.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,65 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * Project:       Geode Frame buffer device driver
+ * </DOC_AMD_STD>
+ */
+
+#include <linux/config.h>
+#ifdef CONFIG_FB_GEODE_DDC
+#if defined(linux)                      /* Linux */
+#ifdef __KERNEL__
+#include <linux/string.h>
+#include <asm/io.h>
+#else
+#include <linux/fs.h>
+#include <asm/mman.h>
+
+/* #include <asm/fcntl.h> */
+#endif /* __KERNEL__ */
+#elif defined(_WIN32)                   /* windows */
+#include <windows.h>
+#endif
+
+/* TODO: generalize debug messages */
+/* undefine the retail message when not CE */
+#if !defined(_WIN32_WCE)
+#define RETAILMSG(_F, _PARA )
+#endif
+
+#include "ddc.h"
+#include "gfx_defs.h"
+/*These variables are global and intiallized by init routines*/
+extern unsigned char *gfx_virt_regptr;
+extern unsigned char *gfx_virt_fbptr;
+extern unsigned char *gfx_virt_vidptr;
+extern unsigned char *gfx_virt_vipptr;
+
+#define PLATFORM_DYNAMIC        1       /* runtime selection */
+#define PLATFORM_5530           1       /* 5530 based platforms */
+#define PLATFORM_x200           1       /* x200 based with ddc on gpio */
+
+/* This include file included to handle the ddc protocols */
+#include "ddc_init.c"
+#endif
diff -uNr linux-2.4.31/drivers/video/nsc/durango.c linux-fb/drivers/video/nsc/durango.c
--- linux-2.4.31/drivers/video/nsc/durango.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/durango.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,517 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * This is the main file used to add Durango graphics support to a software 
+ * project.  The main reason to have a single file include the other files
+ * is that it centralizes the location of the compiler options.  This file
+ * should be tuned for a specific implementation, and then modified as needed
+ * for new Durango releases.  The releases.txt file indicates any updates to
+ * this main file, such as a new definition for a new hardware platform. 
+ *
+ * In other words, this file should be copied from the Durango source files
+ * once when a software project starts, and then maintained as necessary.  
+ * It should not be recopied with new versions of Durango unless the 
+ * developer is willing to tune the file again for the specific project.
+ *
+ * COMPILER OPTIONS
+ * These compiler options specify how the Durango routines are compiled 
+ * for the different hardware platforms.  For best performance, a driver 
+ * would build for a specific platform.  The "dynamic" switches are set 
+ * by diagnostic applications such as Darwin that will run on a variety
+ * of platforms and use the appropriate code at runtime.  Each component
+ * may be separately dynamic, so that a driver has the option of being 
+ * tuned for a specific 2D accelerator, but will still run with a variety
+ * of chipsets. 
+ * </DOC_AMD_STD>
+ */
+
+
+#include <linux/module.h>
+
+#define GFX_DISPLAY_DYNAMIC                     1       /* runtime selection */
+#define GFX_DISPLAY_GU1                         1       /* 1st generation display controller */
+#define GFX_DISPLAY_GU2                         1       /* 2nd generation display controller */
+
+#define GFX_INIT_DYNAMIC            1   /* runtime selection */
+#define GFX_INIT_GU1                1   /* Geode family      */
+#define GFX_INIT_GU2                1   /* Redcloud          */
+
+#define GFX_MSR_DYNAMIC             1   /* runtime selection */
+#define GFX_MSR_REDCLOUD            1   /* Redcloud          */
+
+#define GFX_2DACCEL_DYNAMIC                     1       /* runtime selection */
+#define GFX_2DACCEL_GU1                         1       /* 1st generation 2D accelerator */
+#define GFX_2DACCEL_GU2                         1       /* 2nd generation 2D accelerator */
+
+#define GFX_VIDEO_DYNAMIC                       1       /* runtime selection */
+#define GFX_VIDEO_CS5530                        1       /* support for CS5530 */
+#define GFX_VIDEO_SC1200                        1       /* support for SC1200 */
+#define GFX_VIDEO_REDCLOUD          1   /* support for Redcloud */
+
+#define GFX_VIP_DYNAMIC                         1       /* runtime selection */
+#define GFX_VIP_SC1200                          1       /* support for SC1200 */
+
+#define GFX_DECODER_DYNAMIC                     1       /* runtime selection */
+#define GFX_DECODER_SAA7114                     1       /* Philips SAA7114 decoder */
+
+#define GFX_TV_DYNAMIC                          1       /* runtime selection */
+#define GFX_TV_FS451                            0       /* Focus Enhancements FS450 */
+#define GFX_TV_SC1200                           1       /* SC1200 integrated TV encoder */
+
+#define GFX_I2C_DYNAMIC                         1       /* runtime selection */
+#define GFX_I2C_ACCESS                          1       /* support for ACCESS.BUS */
+#define GFX_I2C_GPIO                            1       /* support for CS5530 GPIOs */
+
+#define GFX_VGA_DYNAMIC                         1       /* runtime selection */
+#define GFX_VGA_GU1                             1       /* 1st generation graphics unit */
+
+#define FB4MB                                   1       /* Set to use 4Mb video ram for Pyramid */
+
+#define GFX_NO_IO_IN_WAIT_MACROS    1   /* Set to remove I/O accesses in GP bit testing */
+
+/* ROUTINES TO READ VALUES
+ * These are routines used by Darwin or other diagnostics to read the 
+ * current state of the hardware.  Display drivers or embedded applications can 
+ * reduce the size of the Durango code by not including these routines. 
+ */
+#define GFX_READ_ROUTINES                       1       /* add routines to read values */
+
+/* HEADER FILE FOR DURANGO ROUTINE DEFINITIONS
+ * Needed since some of the Durango routines call other Durango routines.
+ * Also defines the size of chipset array (GFX_CSPTR_SIZE).
+ */
+#include "gfx_rtns.h"                   /* routine definitions */
+#include "gfx_priv.h"
+
+#ifndef CONFIG_FB_GEODE_TV
+#undef GFX_TV_DYNAMIC
+#undef GFX_TV_FS451
+#undef GFX_TV_SC1200
+#ifndef CONFIG_FB_GEODE_GAL
+#undef GFX_VIP_DYNAMIC
+#undef GFX_VIP_SC1200
+#undef GFX_DECODER_DYNAMIC
+#undef GFX_DECODER_SAA7114
+#undef GFX_I2C_DYNAMIC
+#undef GFX_I2C_ACCESS
+#undef GFX_I2C_GPIO
+#endif
+#endif
+
+/* VARIABLES USED FOR RUNTIME SELECTION
+ * If part of the graphics subsystem is declared as dynamic, then the 
+ * following variables are used to specify which platform has been detected.
+ * The variables are set in the "gfx_detect_cpu" routine.  The values should 
+ * be bit flags to allow masks to be used to check for multiple platforms.
+ */
+
+#if GFX_DISPLAY_DYNAMIC
+int gfx_display_type = 0;
+#endif
+
+#if GFX_INIT_DYNAMIC
+int gfx_init_type = 0;
+#endif
+
+#if GFX_MSR_DYNAMIC
+int gfx_msr_type = 0;
+#endif
+
+#if GFX_2DACCEL_DYNAMIC
+int gfx_2daccel_type = 0;
+#endif
+
+#if GFX_VIDEO_DYNAMIC
+int gfx_video_type = 0;
+#endif
+
+#if GFX_VIP_DYNAMIC
+int gfx_vip_type = 0;
+#endif
+
+#if GFX_DECODER_DYNAMIC
+int gfx_decoder_type = 0;
+#endif
+
+#if GFX_TV_DYNAMIC
+int gfx_tv_type = 0;
+#endif
+
+#if GFX_I2C_DYNAMIC
+int gfx_i2c_type = 0;
+#endif
+
+#if GFX_VGA_DYNAMIC
+int gfx_vga_type = 0;
+#endif
+
+#ifndef _XOPEN_SOURCE
+#define xf86DrvMsg(a,b,format, args...) printk(format, ##args)
+#endif
+
+/* DEFINE POINTERS TO MEMORY MAPPED REGIONS
+ * These pointers are used by the Durango routines to access the hardware. 
+ * The variables must be set by the project's initialization code after
+ * mapping the regions in the appropriate manner. 
+ */
+
+/* DEFINE VIRTUAL ADDRESSES */
+/* Note: These addresses define the starting base expected by all    */
+/*       Durango offsets.  Under an OS that requires these pointers  */
+/*       to be mapped to linear addresses (i.e Windows), it may not  */
+/*       be possible to keep these base offsets.  In these cases,    */
+/*       the addresses are modified to point to the beginning of the */
+/*       relevant memory region and the access macros are adjusted   */
+/*       to subtract the offset from the default base.  For example, */
+/*       the register pointer could be moved to be 0x40008000, while */
+/*       the WRITE_REG* macros are modified to subtract 0x8000 from  */
+/*       the offset.                                                 */
+
+unsigned char *gfx_virt_regptr = (unsigned char *)0x40000000;
+unsigned char *gfx_virt_fbptr = (unsigned char *)0x40800000;
+unsigned char *gfx_virt_vidptr = (unsigned char *)0x40010000;
+unsigned char *gfx_virt_vipptr = (unsigned char *)0x40015000;
+unsigned char *gfx_virt_spptr = (unsigned char *)0x40000000;
+unsigned char *gfx_virt_gpptr = (unsigned char *)0x40000000;
+
+/* DEFINE PHYSICAL ADDRESSES */
+unsigned char *gfx_phys_regptr = (unsigned char *)0x40000000;
+unsigned char *gfx_phys_fbptr = (unsigned char *)0x40800000;
+unsigned char *gfx_phys_vidptr = (unsigned char *)0x40010000;
+unsigned char *gfx_phys_vipptr = (unsigned char *)0x40015000;
+
+/* HEADER FILE FOR GRAPHICS REGISTER DEFINITIONS 
+ * This contains only constant definitions, so it should be able to be 
+ * included in any software project as is.
+ */
+#include "gfx_regs.h"                   /* graphics register definitions */
+
+/* HEADER FILE FOR REGISTER ACCESS MACROS
+ * This file contains the definitions of the WRITE_REG32 and similar macros
+ * used by the Durango routines to access the hardware.  The file assumes 
+ * that the environment can handle 32-bit pointer access.  If this is not
+ * the case, or if there are special requirements, then this header file 
+ * should not be included and the project must define the macros itself.
+ * (A project may define WRITE_REG32 to call a routine, for example).
+ */
+#include "gfx_defs.h"                   /* register access macros */
+
+/* IO MACROS AND ROUTINES
+ * These macros must be defined before the initialization or I2C 
+ * routines will work properly. 
+ */
+
+#if defined(OS_WIN32)                   /* For Windows */
+
+/* VSA II CALL */
+
+void
+gfx_msr_asm_read(unsigned short msrReg, unsigned long msrAddr,
+                 unsigned long *ptrHigh, unsigned long *ptrLow)
+{
+   unsigned long temp1, temp2;
+
+   _asm {
+      mov dx, 0x0AC1C
+            mov eax, 0x0FC530007
+            out dx, eax add dl, 2 mov ecx, msrAddr mov cx, msrReg in ax, dx;
+ EDX:EAX will contain MSR contents.mov temp1, edx mov temp2, eax}
+
+   *ptrHigh = temp1;
+   *ptrLow = temp2;
+}
+
+void
+gfx_msr_asm_write(unsigned short msrReg, unsigned long msrAddr,
+                  unsigned long *ptrHigh, unsigned long *ptrLow)
+{
+   unsigned long temp1 = *ptrHigh;
+   unsigned long temp2 = *ptrLow;
+
+   _asm {
+
+      mov dx, 0x0AC1C
+            mov eax, 0x0FC530007 out dx, eax add dl, 2 mov ecx, msrAddr;
+      ECX contains msrAddr | msrReg mov cx, msrReg;
+      mov ebx, temp1;
+
+      <OR_mask_hi > mov eax, temp2;
+      <OR_mask_hi > mov esi, 0;
+      <AND_mask_hi > mov edi, 0;
+      <AND_mask_lo > out dx, ax;
+   MSR is written at this point}
+}
+
+unsigned char
+gfx_inb(unsigned short port)
+{
+   unsigned char data;
+
+   _asm {
+   pushf mov dx, port in al, dx mov data, al popf}
+   return (data);
+}
+
+unsigned short
+gfx_inw(unsigned short port)
+{
+   unsigned short data;
+
+   _asm {
+   pushf mov dx, port in ax, dx mov data, ax popf}
+   return (data);
+}
+
+unsigned long
+gfx_ind(unsigned short port)
+{
+   unsigned long data;
+
+   _asm {
+   pushf mov dx, port in eax, dx mov data, eax popf}
+   return (data);
+}
+
+void
+gfx_outb(unsigned short port, unsigned char data)
+{
+   _asm {
+   pushf mov al, data mov dx, port out dx, al popf}
+}
+
+void
+gfx_outw(unsigned short port, unsigned short data)
+{
+   _asm {
+   pushf mov ax, data mov dx, port out dx, ax popf}
+}
+
+void
+gfx_outd(unsigned short port, unsigned long data)
+{
+   _asm {
+   pushf mov eax, data mov dx, port out dx, eax popf}
+}
+
+#elif defined(OS_VXWORKS) || defined (OS_LINUX) /* VxWorks and Linux */
+#if defined(OS_LINUX)
+#include "asm/msr.h"
+#endif
+
+void
+gfx_msr_asm_read(unsigned short msrReg, unsigned long msrAddr,
+                 unsigned long *ptrHigh, unsigned long *ptrLow)
+{
+#if 1
+   unsigned long addr, val1, val2;
+
+   addr = msrAddr | (unsigned long)msrReg;
+#if 0
+   __asm__ __volatile__("rdmsr":"=a"(val1), "=d"(val2):"c"(addr));
+#else
+   rdmsr(addr, val1, val2);
+#endif
+
+   *ptrHigh = val2;
+   *ptrLow = val1;
+#endif
+}
+
+void
+gfx_msr_asm_write(unsigned short msrReg, unsigned long msrAddr,
+                  unsigned long *ptrHigh, unsigned long *ptrLow)
+{
+#if 1
+   unsigned long addr, val1, val2;
+
+   val2 = *ptrHigh;
+   val1 = *ptrLow;
+
+#if 1
+   addr = msrAddr | (unsigned long)msrReg;
+#else
+   addr = (msrAddr & 0xFFFF0000) | (unsigned long)msrReg;
+#endif
+#if 0
+   __asm__ __volatile__("wrmsr"::"c"(addr), "a"(val1), "d"(val2));
+#else
+   wrmsr(addr, val1, val2);
+#endif
+#endif
+}
+
+unsigned char
+gfx_inb(unsigned short port)
+{
+   unsigned char value;
+   __asm__ volatile ("inb %1,%0":"=a" (value):"d"(port));
+
+   return value;
+}
+
+unsigned short
+gfx_inw(unsigned short port)
+{
+   unsigned short value;
+   __asm__ volatile ("in %1,%0":"=a" (value):"d"(port));
+
+   return value;
+}
+
+unsigned long
+gfx_ind(unsigned short port)
+{
+   unsigned long value;
+   __asm__ volatile ("inl %1,%0":"=a" (value):"d"(port));
+
+   return value;
+}
+
+void
+gfx_outb(unsigned short port, unsigned char data)
+{
+   __asm__ volatile ("outb %0,%1"::"a" (data), "d"(port));
+}
+
+void
+gfx_outw(unsigned short port, unsigned short data)
+{
+   __asm__ volatile ("out %0,%1"::"a" (data), "d"(port));
+}
+
+void
+gfx_outd(unsigned short port, unsigned long data)
+{
+   __asm__ volatile ("outl %0,%1"::"a" (data), "d"(port));
+}
+
+#else /* else nothing */
+
+unsigned char
+gfx_inb(unsigned short port)
+{
+   /* ADD OS SPECIFIC IMPLEMENTATION */
+   return (0);
+}
+
+unsigned short
+gfx_inw(unsigned short port)
+{
+   /* ADD OS SPECIFIC IMPLEMENTATION */
+   return (0);
+}
+
+unsigned long
+gfx_ind(unsigned short port)
+{
+   /* ADD OS SPECIFIC IMPLEMENTATION */
+   return (0);
+}
+
+void
+gfx_outb(unsigned short port, unsigned char data)
+{
+   /* ADD OS SPECIFIC IMPLEMENTATION */
+}
+
+void
+gfx_outw(unsigned short port, unsigned short data)
+{
+   /* ADD OS SPECIFIC IMPLEMENTATION */
+}
+
+void
+gfx_outd(unsigned short port, unsigned long data)
+{
+   /* ADD OS SPECIFIC IMPLEMENTATION */
+}
+#endif
+
+#define INB(port) gfx_inb(port)
+#define INW(port) gfx_inw(port)
+#define IND(port) gfx_ind(port)
+#define OUTB(port, data) gfx_outb(port, data)
+#define OUTW(port, data) gfx_outw(port, data)
+#define OUTD(port, data) gfx_outd(port, data)
+
+/* INITIALIZATION ROUTINES 
+ * These routines are used during the initialization of the driver to 
+ * perform such tasks as detecting the type of CPU and video hardware.  
+ * The routines require the use of IO, so the above IO routines need 
+ * to be implemented before the initialization routines will work
+ * properly.
+ */
+
+#include "gfx_init.c"
+
+/* INCLUDE MSR ACCESS ROUTINES */
+
+#include "gfx_msr.c"
+
+/* INCLUDE GRAPHICS ENGINE ROUTINES 
+ * These routines are used to program the 2D graphics accelerator.  If
+ * the project does not use graphics acceleration (direct frame buffer
+ * access only), then this file does not need to be included. 
+ */
+#include "gfx_rndr.c"                   /* graphics engine routines */
+
+/* INCLUDE DISPLAY CONTROLLER ROUTINES 
+ * These routines are used if the display mode is set directly.  If the 
+ * project uses VGA registers to set a display mode, then these files
+ * do not need to be included.
+ */
+#include "gfx_mode.h"                   /* display mode tables */
+#include "gfx_disp.c"                   /* display controller routines */
+
+/* INCLUDE VIDEO OVERLAY ROUTINES
+ * These routines control the video overlay hardware. 
+ */
+#include "gfx_vid.c"                    /* video overlay routines */
+
+/* VIDEO PORT AND VIDEO DECODER ROUTINES
+ * These routines rely on the I2C routines.
+ */
+#include "gfx_vip.c"                    /* video port routines */
+#include "gfx_dcdr.c"                   /* video decoder routines */
+
+/* I2C BUS ACCESS ROUTINES
+ * These routines are used by the video decoder and possibly an 
+ * external TV encoer. 
+ */
+#include "gfx_i2c.c"                    /* I2C bus access routines */
+
+/* TV ENCODER ROUTINES
+ * This file does not need to be included if the system does not
+ * support TV output.
+ */
+#include "gfx_tv.c"                     /* TV encoder routines */
+
+/* VGA ROUTINES
+ * This file is used if setting display modes using VGA registers.
+ */
+#include "gfx_vga.c"                    /* VGA routines */
+
+#include "nsc_regacc.c"
+
+/* END OF FILE */
diff -uNr linux-2.4.31/drivers/video/nsc/fbgen.c linux-fb/drivers/video/nsc/fbgen.c
--- linux-2.4.31/drivers/video/nsc/fbgen.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/fbgen.c	2002-08-03 02:39:45.000000000 +0200
@@ -0,0 +1,468 @@
+/*
+ * linux/drivers/video/fbgen.c -- Generic routines for frame buffer devices
+ *
+ *  Created 3 Jan 1998 by Geert Uytterhoeven
+ *
+ *	2001 - Documented with DocBook
+ *	- Brad Douglas <brad@neruo.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/tty.h>
+#include <linux/fb.h>
+#include <linux/slab.h>
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+
+#include <video/fbcon.h>
+
+static int currcon = 0;
+
+
+/* ---- `Generic' versions of the frame buffer device operations ----------- */
+
+
+/**
+ *	fbgen_get_fix - get fixed part of display
+ *	@fix: fb_fix_screeninfo structure
+ *	@con: virtual console number
+ *	@info: frame buffer info structure
+ *
+ *	Get the fixed information part of the display and place it
+ *	into @fix for virtual console @con on device @info.
+ *
+ *	Returns negative errno on error, or zero on success.
+ *
+ */
+
+int fbgen_get_fix(struct fb_fix_screeninfo *fix, int con, struct fb_info *info)
+{
+    struct fb_info_gen *info2 = (struct fb_info_gen *)info;
+    struct fbgen_hwswitch *fbhw = info2->fbhw;
+    char par[info2->parsize];
+
+    if (con == -1)
+	fbhw->get_par(&par, info2);
+    else {
+	int err;
+
+	if ((err = fbhw->decode_var(&fb_display[con].var, &par, info2)))
+	    return err;
+    }
+    memset(fix, 0, sizeof(struct fb_fix_screeninfo));
+    return fbhw->encode_fix(fix, &par, info2);
+}
+
+
+/**
+ *	fbgen_get_var - get user defined part of display
+ *	@var: fb_var_screeninfo structure
+ *	@con: virtual console number
+ *	@info: frame buffer info structure
+ *
+ *	Get the user defined part of the display and place it into @var
+ *	for virtual console @con on device @info.
+ *
+ *	Returns negative errno on error, or zero for success.
+ *
+ */
+
+int fbgen_get_var(struct fb_var_screeninfo *var, int con, struct fb_info *info)
+{
+    struct fb_info_gen *info2 = (struct fb_info_gen *)info;
+    struct fbgen_hwswitch *fbhw = info2->fbhw;
+    char par[info2->parsize];
+
+    if (con == -1) {
+	fbhw->get_par(&par, info2);
+	fbhw->encode_var(var, &par, info2);
+    } else
+	*var = fb_display[con].var;
+    return 0;
+}
+
+
+/**
+ *	fbgen_set_var - set the user defined part of display
+ *	@var: fb_var_screeninfo user defined part of the display
+ *	@con: virtual console number
+ *	@info: frame buffer info structure
+ *
+ *	Set the user defined part of the display as dictated by @var
+ *	for virtual console @con on device @info.
+ *
+ *	Returns negative errno on error, or zero for success.
+ *
+ */
+
+int fbgen_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *info)
+{
+    struct fb_info_gen *info2 = (struct fb_info_gen *)info;
+    int err;
+    int oldxres, oldyres, oldbpp, oldxres_virtual, oldyres_virtual, oldyoffset;
+    struct fb_bitfield oldred, oldgreen, oldblue;
+
+    if ((err = fbgen_do_set_var(var, con == currcon, info2)))
+	return err;
+    if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
+	oldxres = fb_display[con].var.xres;
+	oldyres = fb_display[con].var.yres;
+	oldxres_virtual = fb_display[con].var.xres_virtual;
+	oldyres_virtual = fb_display[con].var.yres_virtual;
+	oldbpp = fb_display[con].var.bits_per_pixel;
+	oldred = fb_display[con].var.red;
+	oldgreen = fb_display[con].var.green;
+	oldblue = fb_display[con].var.blue;
+	oldyoffset = fb_display[con].var.yoffset;
+	fb_display[con].var = *var;
+	if (oldxres != var->xres || oldyres != var->yres ||
+	    oldxres_virtual != var->xres_virtual ||
+	    oldyres_virtual != var->yres_virtual ||
+	    oldbpp != var->bits_per_pixel ||
+	    (!(memcmp(&oldred, &(var->red), sizeof(struct fb_bitfield)))) || 
+	    (!(memcmp(&oldgreen, &(var->green), sizeof(struct fb_bitfield)))) ||
+	    (!(memcmp(&oldblue, &(var->blue), sizeof(struct fb_bitfield)))) ||
+	    oldyoffset != var->yoffset) {
+	    fbgen_set_disp(con, info2);
+	    if (info->changevar)
+		(*info->changevar)(con);
+	    if ((err = fb_alloc_cmap(&fb_display[con].cmap, 0, 0)))
+		return err;
+	    fbgen_install_cmap(con, info2);
+	}
+    }
+    var->activate = 0;
+    return 0;
+}
+
+
+/**
+ *	fbgen_get_cmap - get the colormap
+ *	@cmap: frame buffer colormap structure
+ *	@kspc: boolean, 0 copy local, 1 put_user() function
+ *	@con: virtual console number
+ *	@info: frame buffer info structure
+ *
+ *	Gets the colormap for virtual console @con and places it into
+ *	@cmap for device @info.
+ *
+ *	Returns negative errno on error, or zero for success.
+ *
+ */
+
+int fbgen_get_cmap(struct fb_cmap *cmap, int kspc, int con,
+		   struct fb_info *info)
+{
+    struct fb_info_gen *info2 = (struct fb_info_gen *)info;
+    struct fbgen_hwswitch *fbhw = info2->fbhw;
+
+    if (con == currcon)			/* current console ? */
+	return fb_get_cmap(cmap, kspc, fbhw->getcolreg, info);
+    else
+	if (fb_display[con].cmap.len)	/* non default colormap ? */
+	    fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2);
+	else {
+	    int size = fb_display[con].var.bits_per_pixel == 16 ? 64 : 256;
+	    fb_copy_cmap(fb_default_cmap(size), cmap, kspc ? 0 : 2);
+	}
+    return 0;
+}
+
+
+/**
+ *	fbgen_set_cmap - set the colormap
+ *	@cmap: frame buffer colormap structure
+ *	@kspc: boolean, 0 copy local, 1 get_user() function
+ *	@con: virtual console number
+ *	@info: frame buffer info structure
+ *
+ *	Sets the colormap @cmap for virtual console @con on
+ *	device @info.
+ *
+ *	Returns negative errno on error, or zero for success.
+ *
+ */
+
+int fbgen_set_cmap(struct fb_cmap *cmap, int kspc, int con,
+		   struct fb_info *info)
+{
+    struct fb_info_gen *info2 = (struct fb_info_gen *)info;
+    struct fbgen_hwswitch *fbhw = info2->fbhw;
+    int err;
+
+    if (!fb_display[con].cmap.len) {	/* no colormap allocated ? */
+	int size = fb_display[con].var.bits_per_pixel == 16 ? 64 : 256;
+	if ((err = fb_alloc_cmap(&fb_display[con].cmap, size, 0)))
+	    return err;
+    }
+    if (con == currcon)			/* current console ? */
+	return fb_set_cmap(cmap, kspc, fbhw->setcolreg, info);
+    else
+	fb_copy_cmap(cmap, &fb_display[con].cmap, kspc ? 0 : 1);
+    return 0;
+}
+
+
+/**
+ *	fbgen_pan_display - pan or wrap the display
+ *	@var: frame buffer user defined part of display
+ *	@con: virtual console number
+ *	@info: frame buffer info structure
+ *
+ *	Pan or wrap virtual console @con for device @info.
+ *
+ *	This call looks only at xoffset, yoffset and the
+ *	FB_VMODE_YWRAP flag in @var.
+ *
+ *	Returns negative errno on error, or zero for success.
+ *
+ */
+
+int fbgen_pan_display(struct fb_var_screeninfo *var, int con,
+		      struct fb_info *info)
+{
+    struct fb_info_gen *info2 = (struct fb_info_gen *)info;
+    struct fbgen_hwswitch *fbhw = info2->fbhw;
+    int xoffset = var->xoffset;
+    int yoffset = var->yoffset;
+    int err;
+
+    if (xoffset < 0 ||
+	xoffset+fb_display[con].var.xres > fb_display[con].var.xres_virtual ||
+	yoffset < 0 ||
+	yoffset+fb_display[con].var.yres > fb_display[con].var.yres_virtual)
+	return -EINVAL;
+    if (con == currcon) {
+	if (fbhw->pan_display) {
+	    if ((err = fbhw->pan_display(var, info2)))
+		return err;
+	} else
+	    return -EINVAL;
+    }
+    fb_display[con].var.xoffset = var->xoffset;
+    fb_display[con].var.yoffset = var->yoffset;
+    if (var->vmode & FB_VMODE_YWRAP)
+	fb_display[con].var.vmode |= FB_VMODE_YWRAP;
+    else
+	fb_display[con].var.vmode &= ~FB_VMODE_YWRAP;
+
+    return 0;
+}
+
+
+/* ---- Helper functions --------------------------------------------------- */
+
+
+/**
+ *	fbgen_do_set_var - change the video mode
+ *	@var: frame buffer user defined part of display
+ *	@isactive: boolean, 0 inactive, 1 active
+ *	@info: generic frame buffer info structure
+ *
+ *	Change the video mode settings for device @info.  If @isactive
+ *	is non-zero, the changes will be activated immediately.
+ *
+ *	Return negative errno on error, or zero for success.
+ *
+ */
+
+int fbgen_do_set_var(struct fb_var_screeninfo *var, int isactive,
+		     struct fb_info_gen *info)
+{
+    struct fbgen_hwswitch *fbhw = info->fbhw;
+    int err, activate;
+    char par[info->parsize];
+
+    if ((err = fbhw->decode_var(var, &par, info)))
+	return err;
+    activate = var->activate;
+    if (((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) && isactive)
+	fbhw->set_par(&par, info);
+    fbhw->encode_var(var, &par, info);
+    var->activate = activate;
+    return 0;
+}
+
+
+/**
+ *	fbgen_set_disp - set generic display
+ *	@con: virtual console number
+ *	@info: generic frame buffer info structure
+ *
+ *	Sets a display on virtual console @con for device @info.
+ *
+ */
+
+void fbgen_set_disp(int con, struct fb_info_gen *info)
+{
+    struct fbgen_hwswitch *fbhw = info->fbhw;
+    struct fb_fix_screeninfo fix;
+    char par[info->parsize];
+    struct display *display;
+
+    if (con >= 0)
+	display = &fb_display[con];
+    else
+	display = info->info.disp;	/* used during initialization */
+
+    if (con == -1)
+	fbhw->get_par(&par, info);
+    else
+	fbhw->decode_var(&fb_display[con].var, &par, info);
+    memset(&fix, 0, sizeof(struct fb_fix_screeninfo));
+    fbhw->encode_fix(&fix, &par, info);
+
+    display->visual = fix.visual;
+    display->type = fix.type;
+    display->type_aux = fix.type_aux;
+    display->ypanstep = fix.ypanstep;
+    display->ywrapstep = fix.ywrapstep;
+    display->line_length = fix.line_length;
+    if (info->fbhw->blank || fix.visual == FB_VISUAL_PSEUDOCOLOR ||
+	fix.visual == FB_VISUAL_DIRECTCOLOR)
+	display->can_soft_blank = 1;
+    else
+	display->can_soft_blank = 0;
+    fbhw->set_disp(&par, display, info);
+#if 0 /* FIXME: generic inverse is not supported yet */
+    display->inverse = (fix.visual == FB_VISUAL_MONO01 ? !inverse : inverse);
+#else
+    display->inverse = fix.visual == FB_VISUAL_MONO01;
+#endif
+}
+
+
+/**
+ *	fbgen_install_cmap - install the current colormap
+ *	@con: virtual console number
+ *	@info: generic frame buffer info structure
+ *
+ *	Installs the current colormap for virtual console @con on
+ *	device @info.
+ *
+ */
+
+void fbgen_install_cmap(int con, struct fb_info_gen *info)
+{
+    struct fbgen_hwswitch *fbhw = info->fbhw;
+    if (con != currcon)
+	return;
+    if (fb_display[con].cmap.len)
+	fb_set_cmap(&fb_display[con].cmap, 1, fbhw->setcolreg, &info->info);
+    else {
+	int size = fb_display[con].var.bits_per_pixel == 16 ? 64 : 256;
+	fb_set_cmap(fb_default_cmap(size), 1, fbhw->setcolreg, &info->info);
+    }
+}
+
+
+/**
+ *	fbgen_update_var - update user defined part of display
+ *	@con: virtual console number
+ *	@info: frame buffer info structure
+ *
+ *	Updates the user defined part of the display ('var'
+ *	structure) on virtual console @con for device @info.
+ *	This function is called by fbcon.c.
+ *
+ *	Returns negative errno on error, or zero for success.
+ *
+ */
+
+int fbgen_update_var(int con, struct fb_info *info)
+{
+    struct fb_info_gen *info2 = (struct fb_info_gen *)info;
+    struct fbgen_hwswitch *fbhw = info2->fbhw;
+    int err;
+
+    if (fbhw->pan_display) {
+        if ((err = fbhw->pan_display(&fb_display[con].var, info2)))
+            return err;
+    }
+    return 0;
+}
+
+
+/**
+ *	fbgen_switch - switch to a different virtual console.
+ *	@con: virtual console number
+ *	@info: frame buffer info structure
+ *
+ *	Switch to virtuall console @con on device @info.
+ *
+ *	Returns zero.
+ *
+ */
+
+int fbgen_switch(int con, struct fb_info *info)
+{
+    struct fb_info_gen *info2 = (struct fb_info_gen *)info;
+    struct fbgen_hwswitch *fbhw = info2->fbhw;
+
+    /* Do we have to save the colormap ? */
+    if (fb_display[currcon].cmap.len)
+	fb_get_cmap(&fb_display[currcon].cmap, 1, fbhw->getcolreg,
+		    &info2->info);
+    fbgen_do_set_var(&fb_display[con].var, 1, info2);
+    currcon = con;
+    /* Install new colormap */
+    fbgen_install_cmap(con, info2);
+    return 0;
+}
+
+
+/**
+ *	fbgen_blank - blank the screen
+ *	@blank: boolean, 0 unblank, 1 blank
+ *	@info: frame buffer info structure
+ *
+ *	Blank the screen on device @info.
+ *
+ */
+
+void fbgen_blank(int blank, struct fb_info *info)
+{
+    struct fb_info_gen *info2 = (struct fb_info_gen *)info;
+    struct fbgen_hwswitch *fbhw = info2->fbhw;
+    u16 black[16];
+    struct fb_cmap cmap;
+
+    if (fbhw->blank && !fbhw->blank(blank, info2))
+	return;
+    if (blank) {
+	memset(black, 0, 16*sizeof(u16));
+	cmap.red = black;
+	cmap.green = black;
+	cmap.blue = black;
+	cmap.transp = NULL;
+	cmap.start = 0;
+	cmap.len = 16;
+	fb_set_cmap(&cmap, 1, fbhw->setcolreg, info);
+    } else
+	fbgen_install_cmap(currcon, info2);
+}
+MODULE_LICENSE("GPL");
+
+
+    /*
+     *  Visible symbols for modules
+     */
+
+EXPORT_SYMBOL(fbgen_get_var);
+EXPORT_SYMBOL(fbgen_get_cmap);
+EXPORT_SYMBOL(fbgen_get_fix);
+EXPORT_SYMBOL(fbgen_set_var);
+EXPORT_SYMBOL(fbgen_set_cmap);
+EXPORT_SYMBOL(fbgen_set_disp);
+EXPORT_SYMBOL(fbgen_install_cmap);
+EXPORT_SYMBOL(fbgen_pan_display);
+EXPORT_SYMBOL(fbgen_update_var);
+EXPORT_SYMBOL(fbgen_do_set_var);
+EXPORT_SYMBOL(fbgen_switch);
+EXPORT_SYMBOL(fbgen_blank);
diff -uNr linux-2.4.31/drivers/video/nsc/gfx/disp_gu1.c linux-fb/drivers/video/nsc/gfx/disp_gu1.c
--- linux-2.4.31/drivers/video/nsc/gfx/disp_gu1.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/gfx/disp_gu1.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,2394 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * This file contains routines for the first generation display controller. 
+ * </DOC_AMD_STD>
+ */
+
+void gu1_enable_compression(void);		            /* private routine definition */
+void gu1_disable_compression(void);		            /* private routine definition */
+void gfx_reset_video(void);				            /* private routine definition */
+int gfx_set_display_control(int sync_polarities);	/* private routine definition */
+int gu1_set_specified_mode(DISPLAYMODE *pMode, int bpp);
+
+/* VIDEO BUFFER SIZE */
+
+unsigned long vid_buf_size = 0;
+int vid_enabled = 0;
+
+/*-----------------------------------------------------------------------------
+ * GU1_DELAY_APPROXIMATE (PRIVATE ROUTINE - NOT PART OF DURANGO API)
+ *
+ * Delay the requested number of milliseconds by reading a register.  This function
+ * generally takes longer than the requested time.
+ *-----------------------------------------------------------------------------*/
+
+#define READS_PER_MILLISECOND 60000L
+
+void gu1_delay_approximate (unsigned long milliseconds)
+{
+	/* ASSUME 300 MHz, 5 CLOCKS PER READ */
+
+	unsigned long loop;
+	loop = milliseconds * READS_PER_MILLISECOND;
+	while (loop-- > 0)
+	{
+		READ_REG32(DC_UNLOCK);
+	}
+}
+
+/*-----------------------------------------------------------------------------
+ * GU1_DELAY_PRECISE (PRIVATE ROUTINE - NOT PART OF DURANGO API)
+ *
+ * Delay the number of milliseconds on a more precise level, varying only by 
+ * 1/10 of a ms.  This function should only be called if an SC1200 is present.
+ *-----------------------------------------------------------------------------*/
+void gu1_delay_precise (unsigned long milliseconds)
+{
+#if GFX_VIDEO_SC1200
+
+#define LOOP 1000
+	unsigned long i, timer_start, timer_end, total_ticks, previous_ticks, temp_ticks;
+
+	/* Get current time */
+	timer_start = IND(SC1200_CB_BASE_ADDR + SC1200_CB_TMVALUE);
+	
+	/* Calculate expected end time */
+	if (INB(SC1200_CB_BASE_ADDR + SC1200_CB_TMCNFG) & SC1200_TMCLKSEL_27MHZ)
+		total_ticks = 27000 * milliseconds;      /* timer resolution is 27 MHz */
+	else
+		total_ticks = 1000 * milliseconds;	    /* timer resolution is 1 MHz */
+		
+	if (total_ticks > ((unsigned long)0xffffffff - timer_start)) /* wrap-around */
+		timer_end = total_ticks - ((unsigned long)0xffffffff - timer_start);
+	else
+		timer_end = timer_start + total_ticks;
+	
+	/* in case of wrap around */
+	if (timer_end < timer_start)
+	{
+		previous_ticks = timer_start;
+		while (1)
+		{
+			temp_ticks = IND(SC1200_CB_BASE_ADDR + SC1200_CB_TMVALUE);
+			if (temp_ticks < previous_ticks)
+				break;
+			else
+				previous_ticks = temp_ticks;
+			for (i = 0; i < LOOP; i++)
+				READ_REG32(DC_UNLOCK);
+		}
+	}
+	/* now the non-wrap around part */
+	while (1)
+	{
+		for (i = 0; i < LOOP; i++)
+			READ_REG32(DC_UNLOCK);
+		if(IND(SC1200_CB_BASE_ADDR + SC1200_CB_TMVALUE) > timer_end)
+			break;
+	}
+
+#endif /* GFX_VIDEO_SC1200 */
+}
+
+/*-----------------------------------------------------------------------------
+ * WARNING!!!! INACCURATE DELAY MECHANISM
+ *
+ * In an effort to keep the code self contained and operating system 
+ * independent, the delay loop just performs reads of a display controller
+ * register.  This time will vary for faster processors.  The delay can always
+ * be longer than intended, only effecting the time of the mode switch 
+ * (obviously want it to still be under a second).  Problems with the hardware
+ * only arise if the delay is not long enough.
+ *
+ * For the SC1200, the high resolution timer can be used as an accurate mechanism
+ * for keeping time. However, in order to avoid a busy loop of IO reads, the
+ * timer is polled in-between busy loops, and therefore the actual delay might
+ * be longer than the requested delay by the time of one busy loop
+ * (which on a 200 MHz system took 95 us)
+ *
+ * There are thus two delay functions which are called from the main API routine.
+ * One is meant to be more precise and should only called if an SC1200 is present.
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu1_delay_milliseconds(unsigned long milliseconds)
+#else
+void gfx_delay_milliseconds(unsigned long milliseconds)
+#endif
+{
+#if GFX_VIDEO_SC1200
+
+#if GFX_VIDEO_DYNAMIC
+	if (gfx_video_type == GFX_VIDEO_TYPE_SC1200)
+	{
+#endif
+		gu1_delay_precise(milliseconds);
+		return;
+#if GFX_VIDEO_DYNAMIC
+	}
+#endif
+
+#endif /* GFX_VIDEO_SC1200 */
+
+	gu1_delay_approximate(milliseconds);
+}
+
+#if GFX_DISPLAY_DYNAMIC
+void gu1_delay_microseconds(unsigned long microseconds)
+#else
+void gfx_delay_microseconds(unsigned long microseconds)
+#endif
+{
+	/* ASSUME 300 MHz, 2 CLOCKS PER INCREMENT */
+
+	unsigned long loop_count = microseconds * 150;
+	
+	while (loop_count-- > 0)
+	{
+		;
+	}
+}
+/*-----------------------------------------------------------------------------
+ * GFX_VIDEO_SHUTDOWN
+ *
+ * This routine disables the display controller output.
+ *-----------------------------------------------------------------------------
+ */
+void gu1_video_shutdown(void)
+{
+	unsigned long unlock;
+	unsigned long gcfg, tcfg;
+
+	/* DISABLE COMPRESSION */
+
+	gu1_disable_compression();
+
+	/* ALSO DISABLE VIDEO */
+	/* Use private "reset video" routine to do all that is needed. */
+	/* SC1200, for example, also disables the alpha blending regions. */
+
+	gfx_reset_video();
+
+	/* UNLOCK THE DISPLAY CONTROLLER REGISTERS */
+
+	unlock = READ_REG32(DC_UNLOCK);
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+
+	/* READ THE CURRENT GX VALUES */
+
+    gcfg = READ_REG32(DC_GENERAL_CFG);
+    tcfg = READ_REG32(DC_TIMING_CFG);
+
+    /* BLANK THE GX DISPLAY AND DISABLE THE TIMING GENERATOR */
+
+	tcfg &= ~((unsigned long)DC_TCFG_BLKE | (unsigned long)DC_TCFG_TGEN);	  
+    WRITE_REG32(DC_TIMING_CFG, tcfg);
+
+	/* DELAY: WAIT FOR PENDING MEMORY REQUESTS */ 
+	/* This delay is used to make sure that all pending requests to the */ 
+	/* memory controller have completed before disabling the FIFO load. */
+
+	gfx_delay_milliseconds(1);
+
+    /* DISABLE DISPLAY FIFO LOAD AND DISABLE COMPRESSION */
+
+    gcfg &= ~(unsigned long)(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
+    WRITE_REG32(DC_GENERAL_CFG, gcfg);
+	WRITE_REG32(DC_UNLOCK, unlock);
+	return;
+}
+
+/*-----------------------------------------------------------------------------
+ * GFX_SET_DISPLAY_BPP
+ *
+ * This routine programs the bpp in the display controller.
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_set_display_bpp(unsigned short bpp)
+#else
+int gfx_set_display_bpp(unsigned short bpp)
+#endif
+{
+    unsigned long ocfg, lock;
+
+	lock = READ_REG32 (DC_UNLOCK);
+	ocfg = READ_REG32 (DC_OUTPUT_CFG) & ~(DC_OCFG_8BPP | DC_OCFG_555);
+
+	/* SET DC PIXEL FORMAT */
+
+	if (bpp == 8) ocfg |= DC_OCFG_8BPP;
+	else if (bpp == 15) ocfg |= DC_OCFG_555;
+	else if (bpp != 16) return GFX_STATUS_BAD_PARAMETER;
+
+	WRITE_REG32 (DC_UNLOCK, DC_UNLOCK_VALUE);
+	WRITE_REG32 (DC_OUTPUT_CFG, ocfg);
+	WRITE_REG32 (DC_UNLOCK, lock);
+
+	/* SET BPP IN GRAPHICS PIPELINE */
+
+	gfx_set_bpp (bpp);
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------------
+ * GFX_SET_SPECIFIED_MODE
+ * This routine uses the parameters in the specified display mode structure
+ * to program the display controller hardware.  
+ *-----------------------------------------------------------------------------
+ */
+int gu1_set_specified_mode(DISPLAYMODE *pMode, int bpp)
+{
+	unsigned long unlock, value;
+	unsigned long gcfg, tcfg, ocfg;
+	unsigned long size, pitch;
+	unsigned long vid_buffer_size;
+	unsigned long hactive, vactive;
+	gbpp = bpp;  
+
+	/* CHECK WHETHER TIMING CHANGE IS ALLOWED */
+	/* Flag used for locking also overrides timing change restriction */
+
+	if (gfx_timing_lock && !(pMode->flags & GFX_MODE_LOCK_TIMING))
+		return GFX_STATUS_ERROR;
+		
+	/* SET GLOBAL FLAG */
+	
+	if (pMode->flags & GFX_MODE_LOCK_TIMING)
+		gfx_timing_lock = 1;
+
+	/* DISABLE COMPRESSION */
+
+	gu1_disable_compression();
+
+	/* ALSO DISABLE VIDEO */
+	/* Use private "reset video" routine to do all that is needed. */
+	/* SC1200, for example, also disables the alpha blending regions. */
+
+	gfx_reset_video();
+
+	/* UNLOCK THE DISPLAY CONTROLLER REGISTERS */
+
+	unlock = READ_REG32(DC_UNLOCK);
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+
+	/* READ THE CURRENT GX VALUES */
+
+    gcfg = READ_REG32(DC_GENERAL_CFG);
+    tcfg = READ_REG32(DC_TIMING_CFG);
+
+    /* BLANK THE GX DISPLAY AND DISABLE THE TIMING GENERATOR */
+
+	tcfg &= ~((unsigned long)DC_TCFG_BLKE | (unsigned long)DC_TCFG_TGEN);	  
+    WRITE_REG32(DC_TIMING_CFG, tcfg);
+
+	/* DELAY: WAIT FOR PENDING MEMORY REQUESTS 
+	 * This delay is used to make sure that all pending requests to the 
+	 * memory controller have completed before disabling the FIFO load.
+     */
+
+	gfx_delay_milliseconds(1);
+	
+    /* DISABLE DISPLAY FIFO LOAD AND DISABLE COMPRESSION */
+
+    gcfg &= ~(unsigned long)(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
+    WRITE_REG32(DC_GENERAL_CFG, gcfg);
+
+	/* CLEAR THE "DCLK_MUL" FIELD */ 
+
+	gcfg &= ~(unsigned long)(DC_GCFG_DDCK | DC_GCFG_DPCK | DC_GCFG_DFCK);
+	gcfg &= ~(unsigned long)DC_GCFG_DCLK_MASK;
+	WRITE_REG32(DC_GENERAL_CFG, gcfg);
+
+	/* SET THE DOT CLOCK FREQUENCY */
+	/* Mask off the divide by two bit (bit 31) */
+
+	gfx_set_clock_frequency(pMode->frequency & 0x7FFFFFFF);
+
+	/* DELAY: WAIT FOR THE PLL TO SETTLE */
+	/* This allows the dot clock frequency that was just set to settle. */
+
+	gfx_delay_milliseconds(1);
+
+	/* SET THE "DCLK_MUL" FIELD OF DC_GENERAL_CFG */
+	/* The GX hardware divides the dot clock, so 2x really means that the */ 
+	/* internal dot clock equals the external dot clock. */ 
+
+	if (pMode->frequency & 0x80000000) gcfg |= 0x0040;
+	else gcfg |= 0x0080;
+	WRITE_REG32(DC_GENERAL_CFG, gcfg);
+	
+	/* DELAY: WAIT FOR THE ADL TO LOCK */
+	/* This allows the clock generatation within GX to settle.  This is */
+	/* needed since some of the register writes that follow require that */
+	/* clock to be present. */
+
+	gfx_delay_milliseconds(1);
+
+	/* SET THE GX DISPLAY CONTROLLER PARAMETERS */
+
+	WRITE_REG32(DC_FB_ST_OFFSET, 0);
+	WRITE_REG32(DC_CB_ST_OFFSET, 0);
+	WRITE_REG32(DC_CURS_ST_OFFSET, 0);
+
+	/* SET LINE SIZE AND PITCH */
+	/* Flat panels use the current flat panel line size to    */
+	/* calculate the pitch, but load the true line size       */
+	/* for the mode into the "Frame Buffer Line Size" field   */
+	/* of DC_BUF_SIZE.                                        */
+
+	if (PanelEnable) 
+		size = ModeWidth;
+	else 
+		size = pMode->hactive;
+
+	if (bpp > 8) size <<= 1;
+
+	/* ONLY PYRAMID SUPPORTS 4K LINE SIZE */
+
+	if (size <= 1024)
+	{
+		pitch = 1024;
+
+		/* SPECIAL CASE  */
+		/* Graphics acceleration in 16-bit pixel line double modes */
+		/* requires a pitch of 2048.                               */
+
+		if ((pMode->flags & GFX_MODE_LINE_DOUBLE) && bpp > 8)
+			pitch <<= 1;
+	}
+	else
+	{
+		if (gfx_cpu_version == GFX_CPU_PYRAMID)
+			pitch = (size <= 2048) ? 2048 : 4096;
+		else 
+			pitch = 2048;
+	}
+	WRITE_REG32(DC_LINE_DELTA, pitch >> 2);
+
+	if (PanelEnable) 
+	{
+		size = pMode->hactive;
+		if (bpp > 8) 
+			size <<= 1;
+	}
+
+	/* SAVE PREVIOUSLY STORED VIDEO BUFFER SIZE */
+
+	vid_buffer_size = READ_REG32(DC_BUF_SIZE) & 0x3FFF0000; 
+
+	/* ADD 2 TO SIZE FOR POSSIBLE START ADDRESS ALIGNMENTS */
+
+	WRITE_REG32(DC_BUF_SIZE, ((size >> 3) + 2) | vid_buffer_size);
+
+	/* ALWAYS ENABLE "PANEL" DATA FROM MEDIAGX */
+    /* That is really just the 18 BPP data bus to the companion chip */
+
+	ocfg = DC_OCFG_PCKE | DC_OCFG_PDEL | DC_OCFG_PDEH;
+
+	/* SET PIXEL FORMAT */
+
+	if (bpp == 8) ocfg |= DC_OCFG_8BPP;
+	else if (bpp == 15) ocfg |= DC_OCFG_555;
+
+	/* ENABLE TIMING GENERATOR, SYNCS, AND FP DATA */
+
+	tcfg = DC_TCFG_FPPE | DC_TCFG_HSYE | DC_TCFG_VSYE | DC_TCFG_BLKE |
+		DC_TCFG_TGEN;
+
+	/* SET FIFO PRIORITY, DCLK MULTIPLIER, AND FIFO ENABLE */
+	/* Default 6/5 for FIFO, 2x for DCLK multiplier. */
+
+	gcfg = (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
+
+	/* INCREASE FIFO PRIORITY FOR LARGE MODES */
+
+	if (pMode->hactive==1280 && pMode->vactive==1024) 
+	{
+		if ((bpp == 8) && (pMode->flags & GFX_MODE_85HZ))
+			gcfg = (8l << DC_GCFG_DFHPEL_POS) | (7l << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
+		if ((bpp > 8)  && (pMode->flags & GFX_MODE_75HZ))
+			gcfg = (7l << DC_GCFG_DFHPEL_POS) | (6l << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
+		if ((bpp > 8)  && (pMode->flags & GFX_MODE_85HZ))
+			gcfg = (9l << DC_GCFG_DFHPEL_POS) | (8l << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
+	}
+
+	/* SET DOT CLOCK MULTIPLIER */
+	/* Bit 31 of frequency indicates divide frequency by two */
+
+	if (pMode->frequency & 0x80000000) gcfg |= (1l << DC_GCFG_DCLK_POS);
+	else gcfg |= (2l << DC_GCFG_DCLK_POS);
+
+	/* DIVIDE VIDEO CLOCK */
+	/* CPU core frequencies above 266 MHz will divide the video */
+	/* clock by 4 to ensure that we are running below 150 MHz.  */
+
+	if(gfx_cpu_frequency > 266) 
+		gcfg |= DC_GCFG_VCLK_DIV; 
+
+	/* SET THE PIXEL AND LINE DOUBLE BITS IF NECESSARY */
+
+	hactive = pMode->hactive;
+	vactive = pMode->vactive;
+	gfx_line_double  = 0;
+	gfx_pixel_double = 0;
+
+	if (pMode->flags & GFX_MODE_LINE_DOUBLE)
+	{
+		gcfg |= DC_GCFG_LDBL;
+		hactive <<= 1;
+		
+		/* SET GLOBAL FLAG */
+		
+		gfx_line_double = 1;
+	}
+
+	if (pMode->flags & GFX_MODE_PIXEL_DOUBLE)
+	{
+		tcfg |= DC_TCFG_PXDB;
+		vactive <<= 1;
+
+		/* SET GLOBAL FLAG */
+		
+		gfx_pixel_double = 1;
+	}
+
+	/* COMBINE AND SET TIMING VALUES */
+
+	value = (unsigned long) (hactive - 1) |
+		(((unsigned long) (pMode->htotal - 1)) << 16);
+	WRITE_REG32(DC_H_TIMING_1, value);
+	value = (unsigned long) (pMode->hblankstart - 1) |
+		(((unsigned long) (pMode->hblankend - 1)) << 16);
+	WRITE_REG32(DC_H_TIMING_2, value);
+	value = (unsigned long) (pMode->hsyncstart - 1) |
+		(((unsigned long) (pMode->hsyncend - 1)) << 16);
+	WRITE_REG32(DC_H_TIMING_3, value);
+	WRITE_REG32(DC_FP_H_TIMING, value);
+	value = (unsigned long) (vactive - 1) |
+		(((unsigned long) (pMode->vtotal - 1)) << 16);
+	WRITE_REG32(DC_V_TIMING_1, value);
+	value = (unsigned long) (pMode->vblankstart - 1) |
+		(((unsigned long) (pMode->vblankend - 1)) << 16);
+	WRITE_REG32(DC_V_TIMING_2, value);
+	value = (unsigned long) (pMode->vsyncstart - 1) |
+		(((unsigned long) (pMode->vsyncend - 1)) << 16);
+	WRITE_REG32(DC_V_TIMING_3, value);
+	value = (unsigned long) (pMode->vsyncstart - 2) |
+		(((unsigned long) (pMode->vsyncend - 2)) << 16);
+	WRITE_REG32(DC_FP_V_TIMING, value);
+
+	WRITE_REG32(DC_OUTPUT_CFG, ocfg);
+	WRITE_REG32(DC_TIMING_CFG, tcfg);
+	gfx_delay_milliseconds(1); /* delay after TIMING_CFG */ 
+	WRITE_REG32(DC_GENERAL_CFG, gcfg);
+
+	/* ENABLE FLAT PANEL CENTERING */
+	/* For 640x480 modes displayed with the 9211 within a 800x600 */
+	/* flat panel display, turn on flat panel centering.          */
+
+	if (PanelEnable) 
+	{
+		if (ModeWidth < PanelWidth) 
+		{
+		    tcfg = READ_REG32(DC_TIMING_CFG);
+			tcfg = tcfg | DC_TCFG_FCEN;
+			WRITE_REG32(DC_TIMING_CFG, tcfg);
+			gfx_delay_milliseconds(1); /* delay after TIMING_CFG */
+		}
+	}
+
+	/* CONFIGURE DISPLAY OUTPUT FROM VIDEO PROCESSOR */
+
+	gfx_set_display_control (((pMode->flags & GFX_MODE_NEG_HSYNC) ? 1 : 0) |
+		                     ((pMode->flags & GFX_MODE_NEG_VSYNC) ? 2 : 0));
+
+	/* RESTORE VALUE OF DC_UNLOCK */
+
+	WRITE_REG32(DC_UNLOCK, unlock);
+
+	/* ALSO WRITE GP_BLIT_STATUS FOR PITCH AND 8/18 BPP */
+	/* Remember, only Pyramid supports 4K line pitch    */
+
+	value = 0;
+	if (bpp > 8) value |= BC_16BPP;
+	if( (gfx_cpu_version == GFX_CPU_PYRAMID) && ( pitch > 2048 ))
+		value |= BC_FB_WIDTH_4096;
+	else if (pitch > 1024)
+		value |= BC_FB_WIDTH_2048;
+	WRITE_REG16(GP_BLIT_STATUS, (unsigned short) value);
+
+	return GFX_STATUS_OK;
+
+} /* end gfx_set_specified_mode() */
+
+/*----------------------------------------------------------------------------
+ * GFX_IS_DISPLAY_MODE_SUPPORTED
+ *
+ * This routine sets the specified display mode.
+ *
+ * Returns the index of the mode if successful and mode returned, -1 if the mode 
+ * could not be found.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_is_display_mode_supported(int xres, int yres, int bpp, int hz)
+#else
+int gfx_is_display_mode_supported(int xres, int yres, int bpp, int hz)
+#endif
+{
+	unsigned int mode=0;
+	unsigned long hz_flag = 0, bpp_flag = 0;
+
+	/* SET FLAGS TO MATCH REFRESH RATE */
+
+	if (hz == 56) hz_flag = GFX_MODE_56HZ;
+	else if (hz == 60) hz_flag = GFX_MODE_60HZ;
+	else if (hz == 70) hz_flag = GFX_MODE_70HZ;
+	else if (hz == 72) hz_flag = GFX_MODE_72HZ;
+	else if (hz == 75) hz_flag = GFX_MODE_75HZ;
+	else if (hz == 85) hz_flag = GFX_MODE_85HZ;
+	else return -1;
+
+	/* SET BPP FLAGS TO LIMIT MODE SELECTION */
+
+	if (bpp == 8)  bpp_flag = GFX_MODE_8BPP;
+	else if (bpp == 15) bpp_flag = GFX_MODE_15BPP;
+	else if (bpp == 16) bpp_flag = GFX_MODE_16BPP;
+	else return -1;
+	
+	/* ONLY PYRAMID SUPPORTS 4K PITCH */
+
+	if (gfx_cpu_version != GFX_CPU_PYRAMID && xres > 1024)
+	{
+		if (bpp > 8) 
+			return (-1); /* return with mode not found */
+	}
+
+	/* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */
+
+	for (mode = 0; mode < NUM_GX_DISPLAY_MODES; mode++) {
+		if ((DisplayParams[mode].hactive == (unsigned short)xres) &&
+			(DisplayParams[mode].vactive == (unsigned short)yres) &&
+			(DisplayParams[mode].flags & hz_flag) &&
+			(DisplayParams[mode].flags & bpp_flag)) {
+
+			/* SET THE DISPLAY CONTROLLER FOR THE SELECTED MODE */
+
+			return(mode);
+			}
+		} 
+	return(-1);
+}
+
+/*----------------------------------------------------------------------------
+ * GFX_SET_DISPLAY_MODE
+ *
+ * This routine sets the specified display mode.
+ *
+ * Returns 1 if successful, 0 if mode could not be set.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_set_display_mode(int xres, int yres, int bpp, int hz)
+#else
+int gfx_set_display_mode(int xres, int yres, int bpp, int hz)
+#endif
+{
+	int mode;
+
+	/* DISABLE FLAT PANEL */
+	/* Flat Panel settings are enabled by the function gfx_set_fixed_timings */
+	/* and disabled by gfx_set_display_mode.                                 */
+
+	PanelEnable = 0;
+
+	mode = gfx_is_display_mode_supported(xres, yres, bpp, hz);
+	if(mode >= 0) {
+		if (gu1_set_specified_mode(&DisplayParams[mode], bpp) == GFX_STATUS_OK)
+			return(1);
+	}
+	return(0);
+} 
+
+/*----------------------------------------------------------------------------
+ * GFX_SET_DISPLAY_TIMINGS
+ *
+ * This routine sets the display controller mode using the specified timing
+ * values (as opposed to using the tables internal to Durango).
+ *
+ * Returns GFX_STATUS_OK on success, GFX_STATUS_ERROR otherwise.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_set_display_timings(unsigned short bpp, unsigned short flags, 
+	unsigned short hactive, unsigned short hblankstart, 
+	unsigned short hsyncstart, unsigned short hsyncend,
+	unsigned short hblankend, unsigned short htotal,
+	unsigned short vactive, unsigned short vblankstart, 
+	unsigned short vsyncstart, unsigned short vsyncend,
+	unsigned short vblankend, unsigned short vtotal,
+	unsigned long frequency)
+#else
+int gfx_set_display_timings(unsigned short bpp, unsigned short flags, 
+	unsigned short hactive, unsigned short hblankstart, 
+	unsigned short hsyncstart, unsigned short hsyncend,
+	unsigned short hblankend, unsigned short htotal,
+	unsigned short vactive, unsigned short vblankstart, 
+	unsigned short vsyncstart, unsigned short vsyncend,
+	unsigned short vblankend, unsigned short vtotal,
+	unsigned long frequency)
+#endif
+{
+	/* SET MODE STRUCTURE WITH SPECIFIED VALUES */
+
+	gfx_display_mode.flags = 0;
+	if (flags & 1) gfx_display_mode.flags |= GFX_MODE_NEG_HSYNC;
+	if (flags & 2) gfx_display_mode.flags |= GFX_MODE_NEG_VSYNC;
+	if (flags & 0x1000) gfx_display_mode.flags |= GFX_MODE_LOCK_TIMING;
+	gfx_display_mode.hactive = hactive;
+	gfx_display_mode.hblankstart = hblankstart;
+	gfx_display_mode.hsyncstart = hsyncstart;
+	gfx_display_mode.hsyncend = hsyncend;
+	gfx_display_mode.hblankend = hblankend;
+	gfx_display_mode.htotal = htotal;
+	gfx_display_mode.vactive = vactive;
+	gfx_display_mode.vblankstart = vblankstart;
+	gfx_display_mode.vsyncstart = vsyncstart;
+	gfx_display_mode.vsyncend = vsyncend;
+	gfx_display_mode.vblankend = vblankend;
+	gfx_display_mode.vtotal = vtotal;
+	gfx_display_mode.frequency = frequency;
+
+	/* CALL ROUTINE TO SET MODE */
+
+	return (gu1_set_specified_mode(&gfx_display_mode, bpp));
+}
+
+/*----------------------------------------------------------------------------
+ * GFX_SET_VTOTAL
+ *
+ * This routine sets the display controller vertical total to
+ * "vtotal". As a side effect it also sets vertical blank end.
+ * It should be used when only this value needs to be changed,
+ * due to speed considerations.
+ *
+ * Note: it is the caller's responsibility to make sure that
+ * a legal vtotal is used, i.e. that "vtotal" is greater than or
+ * equal to vsync end.
+ *
+ * Always returns 0.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_set_vtotal(unsigned short vtotal)
+#else
+int gfx_set_vtotal(unsigned short vtotal)
+#endif
+{
+	unsigned long unlock, tcfg, timing1, timing2;
+	
+	/* UNLOCK THE DISPLAY CONTROLLER REGISTERS */
+
+	unlock = READ_REG32(DC_UNLOCK);
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+
+	/* READ THE CURRENT GX VALUES */
+
+    tcfg = READ_REG32(DC_TIMING_CFG);
+	timing1 = READ_REG32(DC_V_TIMING_1);
+	timing2 = READ_REG32(DC_V_TIMING_2);
+	
+    /* DISABLE THE TIMING GENERATOR */
+					  
+    WRITE_REG32(DC_TIMING_CFG, tcfg &  ~(unsigned long)DC_TCFG_TGEN);
+    
+    /* WRITE NEW TIMING VALUES */
+    
+	WRITE_REG32(DC_V_TIMING_1, (timing1 & 0xffff) | (unsigned long)(vtotal - 1) << 16);
+    WRITE_REG32(DC_V_TIMING_2, (timing2 & 0xffff) | (unsigned long)(vtotal - 1) << 16);
+
+	/* RESTORE GX VALUES */
+
+	WRITE_REG32(DC_TIMING_CFG, tcfg);
+	WRITE_REG32(DC_UNLOCK, unlock);
+
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_pitch
+ *
+ * This routine sets the pitch of the frame buffer to the specified value.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu1_set_display_pitch(unsigned short pitch)
+#else
+void gfx_set_display_pitch(unsigned short pitch)
+#endif
+{
+	unsigned long value = 0;
+	unsigned long lock = READ_REG32(DC_UNLOCK);
+
+	value = READ_REG32(DC_LINE_DELTA) & 0xFFFFF000;
+	value |= (pitch >> 2);
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+	WRITE_REG32(DC_LINE_DELTA, value);
+	WRITE_REG32(DC_UNLOCK, lock);
+
+	/* ALSO UPDATE PITCH IN GRAPHICS ENGINE */
+	/* Pyramid alone supports 4K line pitch */
+
+	value = (unsigned long) READ_REG16(GP_BLIT_STATUS);
+	value &= ~(BC_FB_WIDTH_2048 | BC_FB_WIDTH_4096);
+
+	if((gfx_cpu_version == GFX_CPU_PYRAMID) && ( pitch > 2048 )) 	
+		value |= BC_FB_WIDTH_4096;
+
+	else if( pitch > 1024 ) 
+		value |= BC_FB_WIDTH_2048;
+
+	WRITE_REG16(GP_BLIT_STATUS, (unsigned short) value);	
+	return;
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_offset
+ *
+ * This routine sets the start address of the frame buffer.  It is 
+ * typically used to pan across a virtual desktop (frame buffer larger than 
+ * the displayed screen) or to flip the display between multiple buffers.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu1_set_display_offset(unsigned long offset)
+#else
+void gfx_set_display_offset(unsigned long offset)
+#endif
+{
+	/* UPDATE FRAME BUFFER OFFSET */
+
+	unsigned long lock;
+	lock = READ_REG32(DC_UNLOCK);
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+
+	/* START ADDRESS EFFECTS DISPLAY COMPRESSION */
+	/* Disable compression for non-zero start addresss values.            */
+	/* Enable compression if offset is zero and comression is intended to */
+	/* be enabled from a previous call to "gfx_set_compression_enable".   */
+	/* Compression should be disabled BEFORE the offset is changed        */
+	/* and enabled AFTER the offset is changed.                           */
+	
+	if (offset == 0)
+	{
+		WRITE_REG32(DC_FB_ST_OFFSET, offset);
+		if (gfx_compression_enabled)
+		{
+			/* WAIT FOR THE OFFSET TO BE LATCHED */
+			gfx_wait_vertical_blank ();
+			gu1_enable_compression();
+		}
+	}
+	else
+	{
+		/* ONLY DISABLE COMPRESSION ONCE */
+
+		if (gfx_compression_active)
+			gu1_disable_compression();
+
+		WRITE_REG32(DC_FB_ST_OFFSET, offset);
+	}
+
+	WRITE_REG32(DC_UNLOCK, lock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_palette_entry
+ *
+ * This routine sets an palette entry in the display controller.
+ * A 32-bit X:R:G:B value.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_set_display_palette_entry(unsigned long index, unsigned long palette)
+#else
+int gfx_set_display_palette_entry(unsigned long index, unsigned long palette)
+#endif
+{
+	unsigned long data;
+
+	if (index > 0xFF)
+		return GFX_STATUS_BAD_PARAMETER;
+
+	WRITE_REG32(DC_PAL_ADDRESS, index);
+	data = ((palette >> 2) & 0x0003F) | 
+	   	   ((palette >> 4) & 0x00FC0) |
+		   ((palette >> 6) & 0x3F000);
+	WRITE_REG32(DC_PAL_DATA, data);
+
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_palette
+ *
+ * This routine sets the entire palette in the display controller.
+ * A pointer is provided to a 256 entry table of 32-bit X:R:G:B values.
+ * Restriction:
+ * Due to SC1200 Issue #748 (in Notes DB) this function should be called only
+ * when DCLK is active, i.e PLL is already powered up and genlock is not active.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_set_display_palette(unsigned long *palette)
+#else
+int gfx_set_display_palette(unsigned long *palette)
+#endif
+{
+	unsigned long data, i;
+	WRITE_REG32(DC_PAL_ADDRESS, 0);
+	if (palette)
+	{
+		for (i = 0; i < 256; i++)
+		{
+			/* CONVERT 24 BPP COLOR DATA TO 18 BPP COLOR DATA */
+
+			data = ((palette[i] >> 2) & 0x0003F) | 
+				((palette[i] >> 4) & 0x00FC0) |
+				((palette[i] >> 6) & 0x3F000);
+			WRITE_REG32(DC_PAL_DATA, data);
+		}
+	}
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_cursor_enable
+ *
+ * This routine enables or disables the hardware cursor.  
+ *
+ * WARNING: The cusrsor start offset must be set by setting the cursor 
+ * position before calling this routine to assure that memory reads do not
+ * go past the end of graphics memory (this can hang GXm).
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu1_set_cursor_enable(int enable)
+#else
+void gfx_set_cursor_enable(int enable)
+#endif
+{
+	unsigned long unlock, gcfg;
+	
+	/* SET OR CLEAR CURSOR ENABLE BIT */
+
+	unlock = READ_REG32(DC_UNLOCK);
+	gcfg = READ_REG32(DC_GENERAL_CFG);
+	if (enable) gcfg |= DC_GCFG_CURE;
+	else gcfg &= ~(DC_GCFG_CURE);
+
+	/* WRITE NEW REGISTER VALUE */
+
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+	WRITE_REG32(DC_GENERAL_CFG, gcfg);
+	WRITE_REG32(DC_UNLOCK, unlock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_cursor_colors
+ *
+ * This routine sets the colors of the hardware cursor.
+ * Restriction:
+ * Due to SC1200 Issue #748 (in Notes DB) this function should be called only
+ * when DCLK is active, i.e PLL is already powered up.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu1_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor)
+#else
+void gfx_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor)
+#endif
+{
+	unsigned long value;
+	
+	/* If genlock is enabled DCLK might be disabled in vertical blank. */
+	/* Due to SC1200 Issue #748 in Notes DB this would fail the cursor color settings */
+	/* So Wait for vertical blank to end */
+
+#if GFX_VIDEO_SC1200
+	if (gfx_test_timing_active())
+		while ((gfx_get_vline()) > gfx_get_vactive());
+#endif
+
+	/* SET CURSOR COLORS */
+
+	WRITE_REG32(DC_PAL_ADDRESS, 0x100);
+	value = ((bkcolor & 0x000000FC) >> 2) |
+		((bkcolor & 0x0000FC00) >> (2+8-6)) |
+		((bkcolor & 0x00FC0000) >> (2+16-12));
+	WRITE_REG32(DC_PAL_DATA, value);
+	value = ((fgcolor & 0x000000FC) >> 2) |
+		((fgcolor & 0x0000FC00) >> (2+8-6)) |
+		((fgcolor & 0x00FC0000) >> (2+16-12));
+	WRITE_REG32(DC_PAL_DATA, value);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_cursor_position
+ *
+ * This routine sets the position of the hardware cusror.  The starting
+ * offset of the cursor buffer must be specified so that the routine can 
+ * properly clip scanlines if the cursor is off the top of the screen.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu1_set_cursor_position(unsigned long memoffset, 
+	unsigned short xpos, unsigned short ypos, 
+	unsigned short xhotspot, unsigned short yhotspot)
+#else
+void gfx_set_cursor_position(unsigned long memoffset, 
+	unsigned short xpos, unsigned short ypos, 
+	unsigned short xhotspot, unsigned short yhotspot)
+#endif
+{
+	unsigned long unlock;
+
+	short x, y;
+	short xoffset = 0;
+	short yoffset = 0;
+
+	/* SUPPORT CURSOR IN EMULATED VGA MODES */
+	/* Timings are for twice the resolution */
+
+	if (gfx_pixel_double)
+		xpos <<= 1;
+	if (gfx_line_double)
+		ypos <<= 1;
+
+	x = (short) xpos - (short) xhotspot;
+	y = (short) ypos - (short) yhotspot;
+	if (x < -31) return;
+	if (y < -31) return;
+	if (x < 0) { xoffset = -x; x = 0; }
+	if (y < 0) { yoffset = -y; y = 0; }
+	memoffset += (unsigned long) yoffset << 3;
+
+	if (PanelEnable) {
+		if (( ModeWidth > PanelWidth) || (ModeHeight > PanelHeight)) { 
+			gfx_enable_panning (xpos, ypos);
+			x = x - (short)panelLeft;
+			y = y - (short)panelTop;
+		}
+	}
+
+	/* SET CURSOR POSITION */
+
+	unlock = READ_REG32(DC_UNLOCK);
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+	WRITE_REG32(DC_CURS_ST_OFFSET, memoffset);
+	WRITE_REG32(DC_CURSOR_X, (unsigned long) x |
+		(((unsigned long) xoffset) << 11));
+	WRITE_REG32(DC_CURSOR_Y, (unsigned long) y | 
+		(((unsigned long) yoffset) << 11));
+	WRITE_REG32(DC_UNLOCK, unlock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_cursor_shape32
+ *
+ * This routine loads 32x32 cursor data into the specified location in 
+ * graphics memory.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu1_set_cursor_shape32(unsigned long memoffset, 
+	unsigned long *andmask, unsigned long *xormask)
+#else
+void gfx_set_cursor_shape32(unsigned long memoffset, 
+	unsigned long *andmask, unsigned long *xormask)
+#endif
+{
+	int i;
+	unsigned long value;
+	for (i = 0; i < 32; i++)
+	{
+		/* CONVERT TO 16 BITS AND MASK, 16 BITS XOR MASK PER DWORD */
+
+		value = (andmask[i] & 0xFFFF0000) | (xormask[i] >> 16);
+		WRITE_FB32(memoffset, value);
+		memoffset += 4;
+		value = (andmask[i] << 16) | (xormask[i] & 0x0000FFFF);
+		WRITE_FB32(memoffset, value);
+		memoffset += 4;
+	}
+}
+
+/*---------------------------------------------------------------------------
+ * gu1_enable_compression
+ *
+ * This is a private routine to this module (not exposed in the Durango API).
+ * It enables display compression.
+ *---------------------------------------------------------------------------
+ */
+void gu1_enable_compression(void)
+{
+	int i;
+	unsigned long unlock, gcfg, offset;
+
+	/* DO NOT ENABLE IF START ADDRESS IS NOT ZERO */
+
+	offset = READ_REG32(DC_FB_ST_OFFSET) & 0x003FFFFF;
+	if (offset != 0) return;
+
+	/* DO NOT ENABLE IF WE ARE WITHIN AN EMULATED VGA MODE */
+
+	if (gfx_line_double || gfx_pixel_double)
+		return;
+
+	/* SET GLOBAL INDICATOR */
+
+	gfx_compression_active = 1;
+
+	/* CLEAR DIRTY/VALID BITS IN MEMORY CONTROLLER */
+	/* Software is required to do this before enabling compression. */
+	/* Don't want controller to think that old lines are still valid. */
+
+	for (i = 0; i < 1024; i++)
+	{
+		WRITE_REG32(MC_DR_ADD, i);
+		WRITE_REG32(MC_DR_ACC, 0);
+	}
+
+	/* TURN ON COMPRESSION CONTROL BITS */
+
+	unlock = READ_REG32(DC_UNLOCK);
+	gcfg = READ_REG32(DC_GENERAL_CFG);
+	gcfg |= DC_GCFG_CMPE | DC_GCFG_DECE;
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+	WRITE_REG32(DC_GENERAL_CFG, gcfg);
+	WRITE_REG32(DC_UNLOCK, unlock);
+}
+
+/*---------------------------------------------------------------------------
+ * gu1_disable_compression
+ *
+ * This is a private routine to this module (not exposed in the Durango API).
+ * It disables display compression.
+ *---------------------------------------------------------------------------
+ */
+void gu1_disable_compression(void)
+{
+	unsigned long unlock, gcfg;
+
+	/* SET GLOBAL INDICATOR */
+
+	gfx_compression_active = 0;
+
+	/* TURN OFF COMPRESSION CONTROL BITS */
+
+	unlock = READ_REG32(DC_UNLOCK);
+	gcfg = READ_REG32(DC_GENERAL_CFG);
+	gcfg &= ~(DC_GCFG_CMPE | DC_GCFG_DECE);
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+	WRITE_REG32(DC_GENERAL_CFG, gcfg);
+	WRITE_REG32(DC_UNLOCK, unlock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_compression_enable
+ *
+ * This routine enables or disables display compression.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_set_compression_enable(int enable)
+#else
+int gfx_set_compression_enable(int enable)
+#endif
+{
+	/* SET GLOBAL VARIABLE FOR INTENDED STATE */
+	/* Compression can only be enabled for non-zero start address values. */
+	/* Keep state to enable compression on start address changes. */
+
+	gfx_compression_enabled = enable;
+	if (enable) gu1_enable_compression();
+	else gu1_disable_compression();
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_compression_offset
+ *
+ * This routine sets the base offset for the compression buffer.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_set_compression_offset(unsigned long offset)
+#else
+int gfx_set_compression_offset(unsigned long offset)
+#endif
+{
+	unsigned long lock;
+	
+	/* MUST BE 16-BYTE ALIGNED FOR GXLV */
+
+	if (offset & 0x0F) return(1);
+
+	/* SET REGISTER VALUE */
+
+	lock = READ_REG32(DC_UNLOCK);
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+	WRITE_REG32(DC_CB_ST_OFFSET, offset);
+	WRITE_REG32(DC_UNLOCK, lock);
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_compression_pitch
+ *
+ * This routine sets the pitch, in bytes, of the compression buffer. 
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_set_compression_pitch(unsigned short pitch)
+#else
+int gfx_set_compression_pitch(unsigned short pitch)
+#endif
+{
+	unsigned long lock, line_delta;
+	
+	/* SET REGISTER VALUE */
+
+	lock = READ_REG32(DC_UNLOCK);
+	line_delta = READ_REG32(DC_LINE_DELTA) & 0xFF800FFF;
+	line_delta |= ((unsigned long)pitch << 10l) & 0x007FF000;
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+	WRITE_REG32(DC_LINE_DELTA, line_delta);
+	WRITE_REG32(DC_UNLOCK, lock);
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_compression_size
+ *
+ * This routine sets the line size of the compression buffer, which is the
+ * maximum number of bytes allowed to store a compressed line.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_set_compression_size(unsigned short size)
+#else
+int gfx_set_compression_size(unsigned short size)
+#endif
+{
+	unsigned long lock, buf_size;
+
+	/* SUBTRACT 16 FROM SIZE                          */
+	/* The display controller will actually write     */
+	/* 2 extra QWords.  So, if we assume that "size"  */
+	/* refers to the allocated size, we must subtract */
+	/* 16 bytes.                                      */
+
+	size -= 16;
+	
+	/* SET REGISTER VALUE */
+
+	lock = READ_REG32(DC_UNLOCK);
+	buf_size = READ_REG32(DC_BUF_SIZE) & 0xFFFF01FF;
+	buf_size |= (((size >> 2) + 1) & 0x7F) << 9;
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+	WRITE_REG32(DC_BUF_SIZE, buf_size);
+	WRITE_REG32(DC_UNLOCK, lock);
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_enable (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine enables/disables video on GX.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu1_set_display_video_enable(int enable)
+#else
+void gfx_set_display_video_enable(int enable)
+#endif
+{
+	unsigned long lock, gcfg, buf_size;
+	lock     = READ_REG32 (DC_UNLOCK);
+	gcfg     = READ_REG32 (DC_GENERAL_CFG);
+	buf_size = READ_REG32 (DC_BUF_SIZE);
+
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+
+	vid_enabled = enable;
+
+	/* SET THE BUFFER SIZE TO A NON-ZERO VALUE ONLY WHEN */
+	/* ENABLING VIDEO                                    */
+
+	if (enable)
+	{
+		gcfg |= (DC_GCFG_VIDE | DC_GCFG_VRDY);
+		WRITE_REG32 (DC_GENERAL_CFG, gcfg);
+
+		WRITE_REG32 (DC_BUF_SIZE, (buf_size & 0x0000FFFFl) | vid_buf_size);
+	}
+
+	/* CLEAR THE VIDEO BUFFER SIZE WHEN DISABLING VIDEO  */
+
+	else
+	{
+		gcfg &= ~(DC_GCFG_VIDE);
+		WRITE_REG32 (DC_GENERAL_CFG, gcfg);
+	
+		vid_buf_size = buf_size & 0xFFFF0000l;
+		WRITE_REG32 (DC_BUF_SIZE, buf_size & 0x0000FFFFl);
+	}
+
+	WRITE_REG32(DC_UNLOCK, lock);
+	return;
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_size (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_size".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu1_set_display_video_size(unsigned short width, unsigned short height)
+#else
+void gfx_set_display_video_size(unsigned short width, unsigned short height)
+#endif
+{
+	unsigned long lock, size, value;
+	size = (unsigned long) (width << 1) * (unsigned long) height;
+
+	/* STORE THE VIDEO BUFFER SIZE AS A GLOBAL */
+	
+	vid_buf_size = ((size + 63) >> 6) << 16;
+
+	/* DO NOT SET THE VIDEO SIZE IF VIDEO IS DISABLED */
+
+	if (!vid_enabled)
+		return;
+
+	lock = READ_REG32(DC_UNLOCK);
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+	value = READ_REG32(DC_BUF_SIZE) & 0x0000FFFF;
+	value |= vid_buf_size;
+	WRITE_REG32(DC_BUF_SIZE, value);
+	WRITE_REG32(DC_UNLOCK, lock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_offset (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_offset".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu1_set_display_video_offset(unsigned long offset)
+#else
+void gfx_set_display_video_offset(unsigned long offset)
+#endif
+{
+	unsigned long lock;
+	lock = READ_REG32(DC_UNLOCK);
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+	offset &= 0x003FFFFF;
+	WRITE_REG32(DC_VID_ST_OFFSET, offset);
+	WRITE_REG32(DC_UNLOCK, lock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_priority_high
+ *
+ * This routine controls the x-bus round robin arbitration mechanism.
+ * When enable is TRUE, graphics pipeline requests and non-critical display
+ * controller requests are arbitrated at the same priority as processor
+ * requests. When FALSE processor requests are arbitrated at a higher priority.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu1_set_display_priority_high(int enable)
+#else
+void gfx_set_display_priority_high(int enable)
+#endif
+{
+	unsigned long lock, control;
+	lock = READ_REG32(DC_UNLOCK);
+	control = READ_REG32(MC_MEM_CNTRL1);
+	WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE);
+	if (enable)
+		control |= MC_XBUSARB;
+	else control &= ~(MC_XBUSARB);
+	WRITE_REG32(MC_MEM_CNTRL1, control);
+	WRITE_REG32(DC_UNLOCK, lock);
+	return;
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_test_timing_active
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_test_timing_active(void)
+#else
+int gfx_test_timing_active(void)
+#endif
+{
+	if (READ_REG32(DC_TIMING_CFG) & DC_TCFG_TGEN)
+		return(1);
+	else return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_test_vertical_active
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_test_vertical_active(void)
+#else
+int gfx_test_vertical_active(void)
+#endif
+{
+	if (READ_REG32(DC_TIMING_CFG) & DC_TCFG_VNA)
+		return(0);
+	else return(1);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_wait_vertical_blank
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_wait_vertical_blank(void)
+#else
+int gfx_wait_vertical_blank(void)
+#endif
+{
+	if (gfx_test_timing_active())
+	{
+		while(!gfx_test_vertical_active());
+		while(gfx_test_vertical_active());
+	}
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_enable_panning 
+ *
+ * This routine  enables the panning when the Mode is bigger than the panel
+ * size.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu1_enable_panning(int x, int y)
+#else
+void gfx_enable_panning(int x, int y)
+#endif
+{
+    unsigned long modeBytesPerPixel;
+    unsigned long modeBytesPerScanline = 0;
+    unsigned long startAddress = 0;
+        
+    modeBytesPerPixel    =   (gbpp + 7)/8;
+	modeBytesPerScanline = (((ModeWidth + 1023) / 1024) * 1024) * modeBytesPerPixel;
+
+	/* TEST FOR NO-WORK */
+
+	if (x >= DeltaX && (unsigned short)x < (PanelWidth  + DeltaX) && 
+		y >= DeltaY && (unsigned short)y < (PanelHeight + DeltaY))
+		return;
+
+
+	/* ADJUST PANNING VARIABLES WHEN CURSOR EXCEEDS BOUNDARY       */
+	/* Test the boundary conditions for each coordinate and update */
+	/* all variables and the starting offset accordingly.          */
+	
+	if (x < DeltaX)
+		DeltaX = x;
+
+	else if ((unsigned short)x >= (DeltaX + PanelWidth))
+		DeltaX = x - PanelWidth + 1;
+
+	if (y < DeltaY)
+		DeltaY = y;
+
+	else if ((unsigned short)y >= (DeltaY + PanelHeight))
+		DeltaY = y - PanelHeight + 1; 
+
+
+	/* CALCULATE THE START OFFSET */
+
+	startAddress = (DeltaX * modeBytesPerPixel) + (DeltaY * modeBytesPerScanline);
+	
+	gfx_set_display_offset(startAddress);
+
+
+	/* SET PANEL COORDINATES                    */
+	/* Panel's x position must be DWORD aligned */
+
+    panelTop  = DeltaY;
+	panelLeft = DeltaX * modeBytesPerPixel;
+
+	if (panelLeft & 3)
+		panelLeft = (panelLeft & 0xFFFFFFFC) + 4;
+
+	panelLeft /= modeBytesPerPixel;
+
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_fixed_timings
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp)
+#else
+int gfx_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp)
+#endif
+{
+	unsigned int mode;
+
+	ModeWidth = width;
+	ModeHeight = height;
+	PanelWidth  = (unsigned short)panelResX;
+	PanelHeight = (unsigned short)panelResY;
+	PanelEnable = 1;
+		
+	/* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */
+	for (mode = 0; mode < NUM_FIXED_TIMINGS_MODES; mode++) {
+		if ((FixedParams[mode].xres == width) &&
+			(FixedParams[mode].yres == height) &&
+			(FixedParams[mode].panelresx == panelResX) &&
+			(FixedParams[mode].panelresy == panelResY)) {
+
+			/* SET THE 92xx FOR THE SELECTED MODE */
+			FIXEDTIMINGS *fmode = &FixedParams[mode];
+
+			gfx_set_display_timings(bpp, 3, fmode->hactive,fmode->hblankstart, fmode->hsyncstart, fmode->hsyncend,
+				fmode->hblankend, fmode->htotal, fmode->vactive, fmode->vblankstart, 
+				fmode->vsyncstart,	fmode->vsyncend, fmode->vblankend, fmode->vtotal, fmode->frequency);  										
+	
+			return(1);
+			} /* end if() */
+		} /* end for() */
+
+	return(-1);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_panel_present
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp)
+#else
+int gfx_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp)
+#endif
+{
+	/* SET VALID BPP         */
+	/* 16BPP is the default. */
+
+	if (bpp != 8 && bpp != 15 && bpp != 16)
+		bpp = 16;
+
+	/* RECORD PANEL PARAMETERS */
+	/* This routine does not touch any panel timings.  It is used when custom panel */
+	/* settings are set up in advance by the BIOS or an application, but the        */
+	/* application still requires access to other panel functionality provided by   */
+	/* Durango (i.e. panning).                                                      */
+
+	ModeWidth   = width;
+	ModeHeight  = height;
+	PanelWidth  = (unsigned short)panelResX;
+	PanelHeight = (unsigned short)panelResY;
+	PanelEnable = 1;
+	gbpp        = bpp;
+
+	/* PROGRAM THE BPP IN THE DISPLAY CONTROLLER */
+
+	gfx_set_display_bpp (bpp);
+
+	return(GFX_STATUS_OK);
+}
+
+/*-----------------------------------------------------------------------*
+ * THE FOLLOWING READ ROUTINES ARE ALWAYS INCLUDED:                      *                      
+ * gfx_get_hsync_end, gfx_get_htotal, gfx_get_vsync_end, gfx_get_vtotal  *
+ * are used by the video overlay routines.                               *
+ *                                                                       *
+ * gfx_get_vline and gfx_vactive are used to prevent an issue for the    *
+ * SC1200.                                                               *
+ *                                                                       *
+ * The others are part of the Durango API.                               *
+ *-----------------------------------------------------------------------*/
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_pitch
+ *
+ * This routine returns the current pitch of the frame buffer, in bytes.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_display_pitch(void)
+#else
+unsigned short gfx_get_display_pitch(void)
+#endif
+{
+	unsigned long value;
+	if (gfx_cpu_version == GFX_CPU_PYRAMID) {/* Pyramid update for 4KB line pitch */
+		value = (READ_REG32(DC_LINE_DELTA) & 0x07FF) << 2;
+	} else {
+		value = (READ_REG32(DC_LINE_DELTA) & 0x03FF) << 2;
+	}
+
+	return((unsigned short) value);
+}
+
+/*----------------------------------------------------------------------------
+ * GFX_GET_DISPLAY_DETAILS
+ *
+ * This routine gets the specified display mode.
+ *
+ * Returns 1 if successful, 0 if mode could not be get.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_get_display_details(unsigned int mode, int *xres, int *yres, int *hz)
+#else
+int gfx_get_display_details(unsigned int mode, int *xres, int *yres, int *hz)
+#endif
+{
+	if(mode < NUM_GX_DISPLAY_MODES){
+		if(DisplayParams[mode].flags & GFX_MODE_56HZ)
+			*hz = 56;
+		else if(DisplayParams[mode].flags & GFX_MODE_60HZ)
+			*hz = 60;
+		else if(DisplayParams[mode].flags & GFX_MODE_70HZ)
+			*hz = 70;
+		else if(DisplayParams[mode].flags & GFX_MODE_72HZ)
+			*hz = 72;
+		else if(DisplayParams[mode].flags & GFX_MODE_75HZ)
+			*hz = 75;
+		else if(DisplayParams[mode].flags & GFX_MODE_85HZ)
+			*hz = 85;
+
+		*xres = DisplayParams[mode].hactive;
+		*yres = DisplayParams[mode].vactive;
+
+		return(1);
+	}
+	return(0);
+}
+
+/*----------------------------------------------------------------------------
+ * GFX_GET_DISPLAY_MODE_COUNT
+ *
+ * Returns number of modes supported.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_get_display_mode_count(void)
+#else
+int gfx_get_display_mode_count(void)
+#endif
+{
+	return(NUM_GX_DISPLAY_MODES);
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_get_frame_buffer_line_size
+ *
+ * Returns the current frame buffer line size, in bytes
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu1_get_frame_buffer_line_size(void)
+#else
+unsigned long gfx_get_frame_buffer_line_size(void)
+#endif
+{
+	return ((READ_REG32 (DC_BUF_SIZE) & 0x1FF) << 3);
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_mode_frequency_supported
+ *
+ * This routine examines if the requested mode with pixel frequency is supported.
+ *
+ * Returns >0 if successful , <0 if freq. could not be found and matched.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency)
+#else
+int gfx_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency)
+#endif
+{
+	unsigned int index;
+	unsigned long value;
+	unsigned long bpp_flag = 0;
+
+	bpp_flag = GFX_MODE_8BPP;
+	if (bpp > 8) bpp_flag = GFX_MODE_16BPP;
+
+	for (index = 0; index < NUM_GX_DISPLAY_MODES; index++)
+	{
+		if ((DisplayParams[index].hactive == (unsigned short)xres) &&
+			(DisplayParams[index].vactive == (unsigned short)yres) &&
+			(DisplayParams[index].flags & bpp_flag) &&
+			(DisplayParams[index].frequency == frequency))
+		{
+			int hz=0;
+			value = DisplayParams[index].flags;
+
+			if (value & GFX_MODE_56HZ) hz = 56;
+			else if (value & GFX_MODE_60HZ) hz = 60;
+			else if (value & GFX_MODE_70HZ) hz = 70;
+			else if (value & GFX_MODE_72HZ) hz = 72;
+			else if (value & GFX_MODE_75HZ) hz = 75;
+			else if (value & GFX_MODE_85HZ) hz = 85;
+			return(hz);
+		}
+	}
+	return(-1);
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_refreshrate_from_frequency
+ *
+ * This routine maps the frequency to close match refresh rate
+ *
+ * Returns .
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency)
+#else
+int gfx_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency)
+#endif
+{
+	unsigned int index, closematch=0;
+	unsigned long value;
+	unsigned long bpp_flag = 0;
+	long min, diff;
+	
+	*hz = 60;
+
+	bpp_flag = GFX_MODE_8BPP;
+	if (bpp > 8) bpp_flag = GFX_MODE_16BPP;
+
+	/* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */
+	/* Search the table for the closest frequency (16.16 format). */
+
+	min = 0x7fffffff;
+	for (index = 0; index < NUM_GX_DISPLAY_MODES; index++)
+	{
+		if ((DisplayParams[index].htotal == (unsigned short)xres) &&
+			(DisplayParams[index].vtotal == (unsigned short)yres) &&
+			(DisplayParams[index].flags & bpp_flag)) 
+		{
+			diff = (long)frequency - (long)DisplayParams[index].frequency;
+			if(diff < 0) diff = -diff;
+			
+			if (diff < min)
+			{
+				min = diff; 
+				closematch = index;
+			} 
+		}
+	}
+	
+	value = DisplayParams[closematch].flags;
+
+	if (value & GFX_MODE_56HZ) *hz = 56;
+	else if (value & GFX_MODE_60HZ) *hz = 60;
+	else if (value & GFX_MODE_70HZ) *hz = 70;
+	else if (value & GFX_MODE_72HZ) *hz = 72;
+	else if (value & GFX_MODE_75HZ) *hz = 75;
+	else if (value & GFX_MODE_85HZ) *hz = 85;
+
+	return(1);
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_refreshrate_from_mode
+ *
+ * This routine is identical to the gfx_get_refreshrate_from_frequency,
+ * except that the active timing values are compared instead of the total
+ * values.  Some modes (such as 70Hz and 72Hz) may be confused in this routine.
+ *
+ * Returns .
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency)
+#else
+int gfx_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency)
+#endif
+{
+	unsigned int index, closematch=0;
+	unsigned long value;
+	unsigned long bpp_flag = 0;
+	long min, diff;
+	
+	*hz = 60;
+
+	bpp_flag = GFX_MODE_8BPP;
+	if (bpp > 8) bpp_flag = GFX_MODE_16BPP;
+
+	/* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */
+	/* Search the table for the closest frequency (16.16 format). */
+
+	min = 0x7fffffff;
+	for (index = 0; index < NUM_GX_DISPLAY_MODES; index++)
+	{
+		if ((DisplayParams[index].hactive == (unsigned short)xres) &&
+			(DisplayParams[index].vactive == (unsigned short)yres) &&
+			(DisplayParams[index].flags & bpp_flag)) 
+		{
+			diff = (long)frequency - (long)DisplayParams[index].frequency;
+			if(diff < 0) diff = -diff;
+			
+			if (diff < min)
+			{
+				min = diff; 
+				closematch = index;
+			} 
+		}
+	}
+	
+	value = DisplayParams[closematch].flags;
+
+	if (value & GFX_MODE_56HZ) *hz = 56;
+	else if (value & GFX_MODE_60HZ) *hz = 60;
+	else if (value & GFX_MODE_70HZ) *hz = 70;
+	else if (value & GFX_MODE_72HZ) *hz = 72;
+	else if (value & GFX_MODE_75HZ) *hz = 75;
+	else if (value & GFX_MODE_85HZ) *hz = 85;
+
+	return(1);
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_get_frequency_from_refreshrate
+ *
+ * This routine maps the refresh rate to the closest matching PLL frequency.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency)
+#else
+int gfx_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency)
+#endif
+{
+	unsigned int index;
+	int retval = -1;
+	unsigned long hz_flag  = 0;
+	unsigned long bpp_flag = 0;
+	
+	*frequency = 0;
+
+	if      (hz == 56) hz_flag = GFX_MODE_56HZ;
+	else if (hz == 60) hz_flag = GFX_MODE_60HZ;
+	else if (hz == 70) hz_flag = GFX_MODE_70HZ;
+	else if (hz == 72) hz_flag = GFX_MODE_72HZ;
+	else if (hz == 75) hz_flag = GFX_MODE_75HZ;
+	else if (hz == 85) hz_flag = GFX_MODE_85HZ;
+
+	bpp_flag = GFX_MODE_8BPP;
+	if (bpp > 8) bpp_flag = GFX_MODE_16BPP;
+
+	/* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */
+
+	for (index = 0; index < NUM_GX_DISPLAY_MODES; index++)
+	{
+		if ((DisplayParams[index].hactive == (unsigned short)xres) &&
+			(DisplayParams[index].vactive == (unsigned short)yres) &&
+			(DisplayParams[index].flags & bpp_flag)  &&
+			(DisplayParams[index].flags & hz_flag)) 
+		{
+			*frequency = DisplayParams[index].frequency;
+			retval = 1;
+		}
+	}	
+	return retval;
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_max_supported_pixel_clock
+ *
+ * This routine returns the maximum recommended speed for the pixel clock.  The 
+ * return value is an integer of the format xxxyyy, where xxx.yyy is the maximum
+ * floating point pixel clock speed.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu1_get_max_supported_pixel_clock (void)
+#else
+unsigned long gfx_get_max_supported_pixel_clock (void)
+#endif
+
+{
+	/* ALL CHIPS CAN HANDLE 1280X1024@85HZ - 157.5 MHz */
+	
+	return 157500;
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_get_display_mode
+ *
+ * This routine gets the specified display mode.
+ *
+ * Returns >0 if successful and mode returned, <0 if mode could not be found.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_get_display_mode(int *xres, int *yres, int *bpp, int *hz)
+#else
+int gfx_get_display_mode(int *xres, int *yres, int *bpp, int *hz)
+#endif
+{
+	unsigned int mode=0;
+	unsigned long pll_freq = 0, bpp_flag = 0;
+
+	*xres = gfx_get_hactive();
+	*yres = gfx_get_vactive();
+	*bpp  = gfx_get_display_bpp();
+	pll_freq = gfx_get_clock_frequency();
+
+	/* SUPPORT EMULATED VGA MODES */
+
+	if (gfx_pixel_double)
+		*xres >>= 1;
+
+	if (gfx_line_double)
+		*yres >>= 1;
+
+	/* SET BPP FLAGS TO LIMIT MODE SELECTION */
+
+	bpp_flag = GFX_MODE_8BPP;
+	if (*bpp > 8) bpp_flag = GFX_MODE_16BPP;
+
+	for (mode = 0; mode < NUM_GX_DISPLAY_MODES; mode++) {
+		if ((DisplayParams[mode].hactive == (unsigned short)*xres) &&
+			(DisplayParams[mode].vactive == (unsigned short)*yres) &&
+			(DisplayParams[mode].frequency == pll_freq) &&
+			(DisplayParams[mode].flags & bpp_flag)) {
+
+				pll_freq = DisplayParams[mode].flags;
+
+				if (pll_freq & GFX_MODE_56HZ) *hz = 56;
+				else if (pll_freq & GFX_MODE_60HZ) *hz = 60;
+				else if (pll_freq & GFX_MODE_70HZ) *hz = 70;
+				else if (pll_freq & GFX_MODE_72HZ) *hz = 72;
+				else if (pll_freq & GFX_MODE_75HZ) *hz = 75;
+				else if (pll_freq & GFX_MODE_85HZ) *hz = 85;
+
+				return(1);
+			}
+		} 
+	return(-1);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hactive
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_hactive(void)
+#else
+unsigned short gfx_get_hactive(void)
+#endif
+{
+	return((unsigned short)((READ_REG32(DC_H_TIMING_1) & 0x07F8) + 8));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hsync_start
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_hsync_start(void)
+#else
+unsigned short gfx_get_hsync_start(void)
+#endif
+{
+	return((unsigned short)((READ_REG32(DC_H_TIMING_3) & 0x07F8) + 8));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hsync_end
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_hsync_end(void)
+#else
+unsigned short gfx_get_hsync_end(void)
+#endif
+{
+	return((unsigned short)(((READ_REG32(DC_H_TIMING_3) >> 16) & 0x07F8) + 8));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_htotal
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_htotal(void)
+#else
+unsigned short gfx_get_htotal(void)
+#endif
+{
+	return((unsigned short)(((READ_REG32(DC_H_TIMING_1) >> 16) & 0x07F8) + 8));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vactive
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_vactive(void)
+#else
+unsigned short gfx_get_vactive(void)
+#endif
+{
+	return((unsigned short)((READ_REG32(DC_V_TIMING_1) & 0x07FF) + 1));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vsync_end
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_vsync_end(void)
+#else
+unsigned short gfx_get_vsync_end(void)
+#endif
+{
+	return((unsigned short)(((READ_REG32(DC_V_TIMING_3) >> 16) & 0x07FF) + 1));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vtotal
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_vtotal(void)
+#else
+unsigned short gfx_get_vtotal(void)
+#endif
+{
+	return((unsigned short)(((READ_REG32(DC_V_TIMING_1) >> 16) & 0x07FF) + 1));
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_display_bpp
+ *
+ * This routine returns the current color depth of the active display.
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_display_bpp(void)
+#else
+unsigned short gfx_get_display_bpp(void)
+#endif
+{
+	switch(READ_REG32(DC_OUTPUT_CFG) & 3)
+	{
+		case 0: return(16);
+		case 2: return(15);
+	}
+	return(8);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vline
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_vline(void)
+#else
+unsigned short gfx_get_vline(void)
+#endif
+{
+	unsigned short current_scan_line;
+	
+	/* Read similar value twice to ensure that the value is not transitioning */
+	
+	do    current_scan_line = (unsigned short)READ_REG32(DC_V_LINE_CNT) & 0x07FF;
+	while(current_scan_line != (unsigned short)(READ_REG32(DC_V_LINE_CNT) & 0x07FF));
+		
+	return(current_scan_line);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_display_offset
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu1_get_display_offset(void)
+#else
+unsigned long gfx_get_display_offset(void)
+#endif
+{
+	return(READ_REG32(DC_FB_ST_OFFSET) & 0x003FFFFF);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_cursor_offset
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu1_get_cursor_offset(void)
+#else
+unsigned long gfx_get_cursor_offset(void)
+#endif
+{
+	return(READ_REG32(DC_CURS_ST_OFFSET) & 0x003FFFFF);
+}
+
+
+#if GFX_READ_ROUTINES
+
+/*************************************************************/
+/*  READ ROUTINES  |  INCLUDED FOR DIAGNOSTIC PURPOSES ONLY  */
+/*************************************************************/
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hblank_start
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_hblank_start(void)
+#else
+unsigned short gfx_get_hblank_start(void)
+#endif
+{
+	return((unsigned short)((READ_REG32(DC_H_TIMING_2) & 0x07F8) + 8));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hblank_end
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_hblank_end(void)
+#else
+unsigned short gfx_get_hblank_end(void)
+#endif
+{
+	return((unsigned short)(((READ_REG32(DC_H_TIMING_2) >> 16) & 0x07F8) + 8));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vblank_start
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_vblank_start(void)
+#else
+unsigned short gfx_get_vblank_start(void)
+#endif
+{
+	return((unsigned short)((READ_REG32(DC_V_TIMING_2) & 0x07FF) + 1));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vsync_start
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_vsync_start(void)
+#else
+unsigned short gfx_get_vsync_start(void)
+#endif
+{
+	return((unsigned short)((READ_REG32(DC_V_TIMING_3) & 0x07FF) + 1));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vblank_end
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_vblank_end(void)
+#else
+unsigned short gfx_get_vblank_end(void)
+#endif
+{
+	return((unsigned short)(((READ_REG32(DC_V_TIMING_2) >> 16) & 0x07FF) + 1));
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_display_palette_entry
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_get_display_palette_entry(unsigned long index, unsigned long *palette)
+#else
+int gfx_get_display_palette_entry(unsigned long index, unsigned long *palette)
+#endif
+{
+	unsigned long data;
+
+	if (index > 0xFF)
+		return GFX_STATUS_BAD_PARAMETER;
+
+	WRITE_REG32(DC_PAL_ADDRESS, index);
+	data = READ_REG32(DC_PAL_DATA);
+	data = ((data << 2) & 0x000000FC) |
+		   ((data << 4) & 0x0000FC00) |
+		   ((data << 6) & 0x00FC0000);
+	
+	*palette = data;
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_display_palette
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu1_get_display_palette(unsigned long *palette)
+#else
+void gfx_get_display_palette(unsigned long *palette)
+#endif
+{
+	unsigned long i, data;
+	WRITE_REG32(DC_PAL_ADDRESS, 0);
+	for (i = 0; i < 256; i++)
+	{
+		data = READ_REG32(DC_PAL_DATA);
+		data = ((data << 2) & 0x000000FC) |
+			((data << 4) & 0x0000FC00) |
+			((data << 6) & 0x00FC0000);
+		palette[i] = data;
+	}
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_cursor_enable
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu1_get_cursor_enable(void)
+#else
+unsigned long gfx_get_cursor_enable(void)
+#endif
+{
+	return(READ_REG32(DC_GENERAL_CFG) & DC_GCFG_CURE);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_cursor_position
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu1_get_cursor_position(void)
+#else
+unsigned long gfx_get_cursor_position(void)
+#endif
+{
+	return((READ_REG32(DC_CURSOR_X) & 0x07FF) |
+		((READ_REG32(DC_CURSOR_Y) << 16) & 0x03FF0000));
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_cursor_clip
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu1_get_cursor_clip(void)
+#else
+unsigned long gfx_get_cursor_clip(void)
+#endif
+{
+	return(((READ_REG32(DC_CURSOR_X) >> 11) & 0x01F) |
+		((READ_REG32(DC_CURSOR_Y) << 5) & 0x1F0000));
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_cursor_color
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu1_get_cursor_color(int color)
+#else
+unsigned long gfx_get_cursor_color(int color)
+#endif
+{
+	unsigned long data;
+	if (color) 
+	{
+		WRITE_REG32(DC_PAL_ADDRESS, 0x101);
+	}
+	else
+	{
+		WRITE_REG32(DC_PAL_ADDRESS, 0x100);
+	}
+	data = READ_REG32(DC_PAL_DATA);
+	data = ((data << 6) & 0x00FC0000) |
+		((data << 4) & 0x0000FC00) |
+		((data << 2) & 0x000000FC);
+	return(data);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_compression_enable
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_get_compression_enable(void)
+#else
+int gfx_get_compression_enable(void)
+#endif
+{
+	unsigned long gcfg;
+	gcfg = READ_REG32(DC_GENERAL_CFG);
+	if (gcfg & DC_GCFG_CMPE) return(1);
+	else return(0);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_compression_offset
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu1_get_compression_offset(void)
+#else
+unsigned long gfx_get_compression_offset(void)
+#endif
+{
+	unsigned long offset;
+	offset = READ_REG32(DC_CB_ST_OFFSET) & 0x003FFFFF;
+	return(offset);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_compression_pitch
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_compression_pitch(void)
+#else
+unsigned short gfx_get_compression_pitch(void)
+#endif
+{
+	unsigned short pitch;
+	pitch = (unsigned short) (READ_REG32(DC_LINE_DELTA) >> 12) & 0x07FF;
+	return(pitch << 2);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_compression_size
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu1_get_compression_size(void)
+#else
+unsigned short gfx_get_compression_size(void)
+#endif
+{
+	unsigned short size;
+	size = (unsigned short) ((READ_REG32(DC_BUF_SIZE) >> 9) & 0x7F) - 1;
+	return((size << 2) + 16);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_valid_bit
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_get_valid_bit(int line)
+#else
+int gfx_get_valid_bit(int line)
+#endif
+{
+	int valid;
+	WRITE_REG32(MC_DR_ADD, line);
+	valid = (int)READ_REG32(MC_DR_ACC) & 1;
+	return(valid);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_video_offset (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_get_video_offset".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu1_get_display_video_offset(void)
+#else
+unsigned long gfx_get_display_video_offset(void)
+#endif
+{
+	return(READ_REG32(DC_VID_ST_OFFSET) & 0x003FFFFF);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_video_size (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_get_video_size".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu1_get_display_video_size(void)
+#else
+unsigned long gfx_get_display_video_size(void)
+#endif
+{
+	/* RETURN TOTAL SIZE, IN BYTES */
+
+	return((READ_REG32(DC_BUF_SIZE) >> 10) & 0x000FFFC0);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_display_priority_high
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu1_get_display_priority_high(void)
+#else
+int gfx_get_display_priority_high(void)
+#endif
+{
+	if (READ_REG32(MC_MEM_CNTRL1) & MC_XBUSARB) return(1);
+	else return(0);
+}
+
+#endif /* GFX_READ_ROUTINES */
+
+/* END OF FILE */
diff -uNr linux-2.4.31/drivers/video/nsc/gfx/disp_gu2.c linux-fb/drivers/video/nsc/gfx/disp_gu2.c
--- linux-2.4.31/drivers/video/nsc/gfx/disp_gu2.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/gfx/disp_gu2.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,2603 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * This file contains routines for the second generation display controller.
+ * </DOC_AMD_STD>
+ */
+
+void gu2_enable_compression(void);		            /* private routine definition */
+void gu2_disable_compression(void);		            /* private routine definition */
+int gfx_set_display_control(int sync_polarities);	/* private routine definition */
+void gfx_reset_video (void);
+int gu2_set_specified_mode(DISPLAYMODE *pMode, int bpp);	
+		 
+ /*-----------------------------------------------------------------------------
+ * WARNING!!!! INACCURATE DELAY MECHANISM
+ *
+ * In an effort to keep the code self contained and operating system 
+ * independent, the delay loop just performs reads of a display controller
+ * register.  This time will vary for faster processors.  The delay can always
+ * be longer than intended, only effecting the time of the mode switch 
+ * (obviously want it to still be under a second).  Problems with the hardware
+ * only arise if the delay is not long enough.  
+ *-----------------------------------------------------------------------------
+ */
+
+#define RC_READS_PER_MILLISECOND 15000L
+
+#if GFX_DISPLAY_DYNAMIC
+void gu2_delay_milliseconds(unsigned long milliseconds)
+#else
+void gfx_delay_milliseconds(unsigned long milliseconds)
+#endif
+{
+	/* ASSUME 300 MHZ 20 CLOCKS PER READ */
+
+	unsigned long loop;
+	loop = milliseconds * RC_READS_PER_MILLISECOND;
+	while (loop-- > 0)
+	{
+		READ_REG32 (MDC_UNLOCK);
+	}
+}
+
+#if GFX_DISPLAY_DYNAMIC
+void gu2_delay_microseconds(unsigned long microseconds)
+#else
+void gfx_delay_microseconds(unsigned long microseconds)
+#endif
+{
+	/* ASSUME 400 MHz, 2 CLOCKS PER INCREMENT */
+
+
+	unsigned long loop_count = microseconds * 15;
+	
+	while (loop_count-- > 0)
+	{
+		READ_REG32 (MDC_UNLOCK);
+	}
+}
+	
+/*-----------------------------------------------------------------------------
+ * GFX_SET_DISPLAY_BPP
+ *
+ * This routine programs the bpp in the display controller.
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_set_display_bpp(unsigned short bpp)
+#else
+int gfx_set_display_bpp(unsigned short bpp)
+#endif
+{
+    unsigned long dcfg, lock;
+
+	dcfg = READ_REG32 (MDC_DISPLAY_CFG) & ~(MDC_DCFG_DISP_MODE_MASK | MDC_DCFG_16BPP_MODE_MASK);
+	lock = READ_REG32 (MDC_UNLOCK);
+
+	switch (bpp)
+	{
+	    case 12: dcfg |= (MDC_DCFG_DISP_MODE_16BPP | MDC_DCFG_12BPP); break;
+		case 15: dcfg |= (MDC_DCFG_DISP_MODE_16BPP | MDC_DCFG_15BPP); break;
+		case 16: dcfg |= (MDC_DCFG_DISP_MODE_16BPP | MDC_DCFG_16BPP); break;
+		case 32: dcfg |= (MDC_DCFG_DISP_MODE_24BPP);  break;
+		case 8:  dcfg |= (MDC_DCFG_DISP_MODE_8BPP);   break;
+		default: return GFX_STATUS_BAD_PARAMETER;
+	}
+
+	WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32 (MDC_DISPLAY_CFG, dcfg);
+	WRITE_REG32 (MDC_UNLOCK, lock);
+
+	/* SET BPP IN GRAPHICS PIPELINE */
+
+	gfx_set_bpp (bpp);
+
+	return 0;
+}
+
+/*-----------------------------------------------------------------------------
+ * gu2_set_specified_mode (private routine)
+ * This routine uses the parameters in the specified display mode structure
+ * to program the display controller hardware.  
+ *-----------------------------------------------------------------------------
+ */
+int gu2_set_specified_mode(DISPLAYMODE *pMode, int bpp)
+{
+	unsigned long unlock, value;
+	unsigned long gcfg, dcfg;
+	unsigned long size, pitch;
+	unsigned long vid_buf_size;
+	unsigned long bpp_mask, temp, dv_size;
+	
+	/* CHECK WHETHER TIMING CHANGE IS ALLOWED */
+	/* Flag used for locking also overrides timing change restriction */
+
+	if (gfx_timing_lock && !(pMode->flags & GFX_MODE_LOCK_TIMING))
+		return GFX_STATUS_ERROR;
+	
+	/* CLEAR PANNING OFFSETS */
+
+	DeltaX = 0;
+	DeltaY = 0;
+	panelLeft = 0;
+	panelTop  = 0;
+
+	/* SET GLOBAL FLAG */
+	
+	if (pMode->flags & GFX_MODE_LOCK_TIMING)
+		gfx_timing_lock = 1;
+
+	/* CHECK FOR VALID BPP                          */
+	/* As this function can be called directly from */
+	/* gfx_set_display_timings, we must correct any */
+	/* invalid bpp settings.                        */
+
+	switch (bpp)
+	{
+	    case 12: bpp_mask = 0x00000900; break;
+		case 15: bpp_mask = 0x00000500; break;
+		case 16: bpp_mask = 0x00000100; break;
+		case 32: bpp_mask = 0x00000200; break;
+		default: bpp_mask = 0x00000000; bpp = 8; break;
+	}
+
+	gbpp = bpp;
+
+	/* DISABLE COMPRESSION */
+
+	gu2_disable_compression();
+
+	/* ALSO DISABLE VIDEO */
+	/* Use private "reset video" routine to do all that is needed. */
+	/* SC1200, for example, also disables the alpha blending regions. */
+
+	gfx_reset_video();
+
+	/* UNLOCK THE DISPLAY CONTROLLER REGISTERS */
+
+	unlock = READ_REG32 (MDC_UNLOCK);
+	WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE);
+
+	/* READ THE CURRENT REGISTER VALUES */
+
+    gcfg = READ_REG32 (MDC_GENERAL_CFG);
+    dcfg = READ_REG32 (MDC_DISPLAY_CFG);
+
+    /* BLANK THE DISPLAY IN THE DISPLAY FILTER */
+
+	gfx_set_crt_enable (0);
+
+    /* DISABLE THE TIMING GENERATOR */
+
+    dcfg &= ~(unsigned long)MDC_DCFG_TGEN;						  
+    WRITE_REG32 (MDC_DISPLAY_CFG, dcfg);
+	
+	/* DELAY: WAIT FOR PENDING MEMORY REQUESTS                            */
+	/* This delay is used to make sure that all pending requests to the   */
+	/* memory controller have completed before disabling the FIFO load.   */
+    
+	gfx_delay_milliseconds(5);
+
+    /* DISABLE DISPLAY FIFO LOAD */
+
+    gcfg &= ~(unsigned long)MDC_GCFG_DFLE;
+    WRITE_REG32 (MDC_GENERAL_CFG, gcfg);
+
+	/* PRESERVE VIDEO INFORMATION */
+
+	gcfg &= (unsigned long)(MDC_GCFG_YUVM | MDC_GCFG_VDSE);
+	dcfg  = 0;
+
+	/* SET THE DOT CLOCK FREQUENCY             */
+	/* Mask off the divide by two bit (bit 31) */
+
+	gfx_set_clock_frequency(pMode->frequency & 0x7FFFFFFF);
+
+	/* DELAY: WAIT FOR THE PLL TO SETTLE */
+	/* This allows the dot clock frequency that was just set to settle. */
+
+	gfx_delay_milliseconds(10);
+
+	/* SET THE GX DISPLAY CONTROLLER PARAMETERS */
+
+	WRITE_REG32 (MDC_FB_ST_OFFSET,   0);
+	WRITE_REG32 (MDC_CB_ST_OFFSET,   0);
+	WRITE_REG32 (MDC_CURS_ST_OFFSET, 0);
+	WRITE_REG32 (MDC_ICON_ST_OFFSET, 0);
+
+	/* SET LINE SIZE AND PITCH */
+	/* 1. Flat Panels must use the mode width and not  */
+	/*    the timing width to set the pitch.           */
+	/* 2. Mode sets will use a pitch that is aligned   */
+	/*    on a 1K boundary to preserve legacy.  The    */
+	/*    pitch can be overridden by a subsequent call */
+	/*    to gfx_set_display_pitch.                    */
+
+	if (PanelEnable) 
+		size = ModeWidth;
+	else 
+		size = pMode->hactive;
+	
+	if (bpp > 8)  size <<= 1;
+	if (bpp > 16) size <<= 1;
+		
+	pitch = 1024;
+	dv_size = MDC_DV_LINE_SIZE_1024;
+	
+	if (size > 1024)
+	{
+		pitch = 2048;
+		dv_size = MDC_DV_LINE_SIZE_2048;
+	}
+	if (size > 2048) 
+	{
+		pitch = 4096;
+		dv_size = MDC_DV_LINE_SIZE_4096;
+	}
+	if (size > 4096)
+	{
+		pitch = 8192;
+		dv_size = MDC_DV_LINE_SIZE_8192;
+	}
+	WRITE_REG32(MDC_GFX_PITCH, pitch >> 3);
+
+	/* WRITE DIRTY/VALID CONTROL WITH LINE LENGTH */
+
+	temp = READ_REG32 (MDC_DV_CTL);
+	WRITE_REG32 (MDC_DV_CTL, (temp & ~MDC_DV_LINE_SIZE_MASK) | dv_size);
+
+	if (PanelEnable) 
+	{
+		size = pMode->hactive;
+		if (bpp > 8)  size <<= 1;
+		if (bpp > 16) size <<= 1;
+	}
+
+	/* SAVE PREVIOUSLY STORED VIDEO LINE SIZE */
+
+	vid_buf_size = READ_REG32(MDC_LINE_SIZE) & 0xFF000000; 
+
+	/* ADD 2 TO SIZE FOR POSSIBLE START ADDRESS ALIGNMENTS */
+
+	WRITE_REG32 (MDC_LINE_SIZE, ((size >> 3) + 2) | vid_buf_size);
+
+
+	/* ALWAYS ENABLE VIDEO AND GRAPHICS DATA            */
+	/* These bits are relics from a previous design and */
+	/* should always be enabled.                        */
+
+	dcfg |= (unsigned long)(MDC_DCFG_VDEN | MDC_DCFG_GDEN);
+	
+	/* SET PIXEL FORMAT */
+
+	dcfg |= bpp_mask;
+
+	/* ENABLE TIMING GENERATOR, TIM. REG. UPDATES, PALETTE BYPASS */
+	/* AND VERT. INT. SELECT                                      */
+
+	dcfg |= (unsigned long)(MDC_DCFG_TGEN | MDC_DCFG_TRUP | MDC_DCFG_PALB | MDC_DCFG_VISL);
+
+    /* DISABLE ADDRESS MASKS */
+    
+    dcfg |= MDC_DCFG_A20M;
+    dcfg |= MDC_DCFG_A18M;
+
+	/* SET FIFO PRIORITIES AND DISPLAY FIFO LOAD ENABLE     */
+	/* Set the priorities higher for high resolution modes. */
+
+	if (pMode->hactive > 1024 || bpp == 32)
+		gcfg |= 0x000A901;
+	else
+		gcfg |= 0x0006501;
+
+    
+	/* ENABLE FLAT PANEL CENTERING                          */
+	/* For panel modes having a resolution smaller than the */
+	/* panel resolution, turn on data centering.            */
+
+	if (PanelEnable && ModeWidth < PanelWidth) 
+	    dcfg |= MDC_DCFG_DCEN;
+
+	/* COMBINE AND SET TIMING VALUES */
+
+	value = (unsigned long) (pMode->hactive - 1) |
+		  (((unsigned long) (pMode->htotal  - 1)) << 16);
+	WRITE_REG32(MDC_H_ACTIVE_TIMING, value);
+	value = (unsigned long) (pMode->hblankstart - 1) |
+		  (((unsigned long) (pMode->hblankend   - 1)) << 16);
+	WRITE_REG32(MDC_H_BLANK_TIMING, value);
+	value = (unsigned long) (pMode->hsyncstart - 1) |
+		  (((unsigned long) (pMode->hsyncend   - 1)) << 16);
+	WRITE_REG32(MDC_H_SYNC_TIMING, value);
+	value = (unsigned long) (pMode->vactive - 1) |
+		  (((unsigned long) (pMode->vtotal  - 1)) << 16);
+	WRITE_REG32(MDC_V_ACTIVE_TIMING, value);
+	value = (unsigned long) (pMode->vblankstart - 1) |
+		  (((unsigned long) (pMode->vblankend - 1)) << 16);
+	WRITE_REG32(MDC_V_BLANK_TIMING, value);
+	value = (unsigned long) (pMode->vsyncstart - 1) |
+		  (((unsigned long) (pMode->vsyncend - 1)) << 16);
+	WRITE_REG32(MDC_V_SYNC_TIMING, value);
+		
+	WRITE_REG32 (MDC_DISPLAY_CFG, dcfg);
+	WRITE_REG32 (MDC_GENERAL_CFG, gcfg);	
+
+	/* CONFIGURE DISPLAY OUTPUT FROM VIDEO PROCESSOR */
+
+	gfx_set_display_control (((pMode->flags & GFX_MODE_NEG_HSYNC) ? 1 : 0) |
+		                     ((pMode->flags & GFX_MODE_NEG_VSYNC) ? 2 : 0));
+
+	/* RESTORE VALUE OF MDC_UNLOCK */
+
+	WRITE_REG32(MDC_UNLOCK, unlock);
+
+	/* RESET THE PITCH VALUES IN THE GP */
+	
+	gfx_reset_pitch ((unsigned short)pitch);
+
+	gfx_set_bpp ((unsigned short)bpp);
+
+	return GFX_STATUS_OK;
+}
+
+ /*----------------------------------------------------------------------------
+ * GFX_IS_DISPLAY_MODE_SUPPORTED
+ *
+ * This routine sets the specified display mode.
+ *
+ * Returns 1 if successful, 0 if mode could not be set.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_is_display_mode_supported(int xres, int yres, int bpp, int hz)
+#else
+int gfx_is_display_mode_supported(int xres, int yres, int bpp, int hz)
+#endif
+{
+	unsigned int mode;
+	unsigned long hz_flag = 0, bpp_flag = 0;
+
+	/* SET FLAGS TO MATCH REFRESH RATE */
+
+	if (hz == 56) hz_flag = GFX_MODE_56HZ;
+	if (hz == 60) hz_flag = GFX_MODE_60HZ;
+	if (hz == 70) hz_flag = GFX_MODE_70HZ;
+	if (hz == 72) hz_flag = GFX_MODE_72HZ;
+	if (hz == 75) hz_flag = GFX_MODE_75HZ;
+	if (hz == 85) hz_flag = GFX_MODE_85HZ;
+	
+	/* SET BPP FLAGS TO LIMIT MODE SELECTION */
+
+	switch (bpp)
+	{
+	    case 8:  bpp_flag = GFX_MODE_8BPP;  break;
+		case 12: bpp_flag = GFX_MODE_12BPP; break;
+		case 15: bpp_flag = GFX_MODE_15BPP; break;
+		case 16: bpp_flag = GFX_MODE_16BPP; break;
+		case 32: bpp_flag = GFX_MODE_24BPP; break;
+		default: return (-1);
+	}
+
+	/* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */
+
+	for (mode = 0; mode < NUM_RC_DISPLAY_MODES; mode++) 
+	{
+		if ((DisplayParams[mode].hactive == (unsigned short)xres) &&
+			(DisplayParams[mode].vactive == (unsigned short)yres) &&
+			(DisplayParams[mode].flags & hz_flag) &&
+			(DisplayParams[mode].flags & bpp_flag)) 
+		{
+
+			/* REDCLOUD DOES NOT SUPPORT EMULATED VGA MODES */
+
+			if ((DisplayParams[mode].flags & GFX_MODE_PIXEL_DOUBLE) ||
+				(DisplayParams[mode].flags & GFX_MODE_LINE_DOUBLE))
+				continue;
+
+			/* SET THE DISPLAY CONTROLLER FOR THE SELECTED MODE */
+
+			return(mode);
+		}
+	} 
+	return(-1);
+} 
+
+/*----------------------------------------------------------------------------
+ * gfx_set_display_mode
+ *
+ * This routine sets the specified display mode.
+ *
+ * Returns 1 if successful, 0 if mode could not be set.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_set_display_mode(int xres, int yres, int bpp, int hz)
+#else
+int gfx_set_display_mode(int xres, int yres, int bpp, int hz)
+#endif
+{
+	int mode;
+
+	/* DISABLE FLAT PANEL */
+	/* Flat Panel settings are enabled by the function gfx_set_fixed_timings */
+	/* and disabled by gfx_set_display_mode.                                 */
+
+	PanelEnable = 0;
+
+	mode = gfx_is_display_mode_supported(xres, yres, bpp, hz);
+	if(mode >= 0)
+	{
+		if (gu2_set_specified_mode(&DisplayParams[mode], bpp) == GFX_STATUS_OK)
+			return(1);
+	}
+	return(0);
+} 
+
+/*----------------------------------------------------------------------------
+ * GFX_SET_DISPLAY_TIMINGS
+ *
+ * This routine sets the display controller mode using the specified timing
+ * values (as opposed to using the tables internal to Durango).
+ *
+ * Returns GFX_STATUS_OK ON SUCCESS, GFX_STATUS_ERROR otherwise.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_set_display_timings(unsigned short bpp, unsigned short flags, 
+	unsigned short hactive, unsigned short hblankstart, 
+	unsigned short hsyncstart, unsigned short hsyncend,
+	unsigned short hblankend, unsigned short htotal,
+	unsigned short vactive, unsigned short vblankstart, 
+	unsigned short vsyncstart, unsigned short vsyncend,
+	unsigned short vblankend, unsigned short vtotal,
+	unsigned long frequency)
+#else
+int gfx_set_display_timings(unsigned short bpp, unsigned short flags, 
+	unsigned short hactive, unsigned short hblankstart, 
+	unsigned short hsyncstart, unsigned short hsyncend,
+	unsigned short hblankend, unsigned short htotal,
+	unsigned short vactive, unsigned short vblankstart, 
+	unsigned short vsyncstart, unsigned short vsyncend,
+	unsigned short vblankend, unsigned short vtotal,
+	unsigned long frequency)
+#endif
+{
+	/* SET MODE STRUCTURE WITH SPECIFIED VALUES */
+
+	gfx_display_mode.flags = 0;
+	if (flags & 1) gfx_display_mode.flags |= GFX_MODE_NEG_HSYNC;
+	if (flags & 2) gfx_display_mode.flags |= GFX_MODE_NEG_VSYNC;
+	if (flags & 0x1000) gfx_display_mode.flags |= GFX_MODE_LOCK_TIMING;
+	gfx_display_mode.hactive = hactive;
+	gfx_display_mode.hblankstart = hblankstart;
+	gfx_display_mode.hsyncstart = hsyncstart;
+	gfx_display_mode.hsyncend = hsyncend;
+	gfx_display_mode.hblankend = hblankend;
+	gfx_display_mode.htotal = htotal;
+	gfx_display_mode.vactive = vactive;
+	gfx_display_mode.vblankstart = vblankstart;
+	gfx_display_mode.vsyncstart = vsyncstart;
+	gfx_display_mode.vsyncend = vsyncend;
+	gfx_display_mode.vblankend = vblankend;
+	gfx_display_mode.vtotal = vtotal;
+	gfx_display_mode.frequency = frequency;
+
+	/* CALL ROUTINE TO SET MODE */
+
+	return (gu2_set_specified_mode(&gfx_display_mode, bpp));
+}
+
+/*----------------------------------------------------------------------------
+ * GFX_SET_VTOTAL
+ *
+ * This routine sets the display controller vertical total to
+ * "vtotal". As a side effect it also sets vertical blank end.
+ * It should be used when only this value needs to be changed,
+ * due to speed considerations.
+ *
+ * Note: it is the caller's responsibility to make sure that
+ * a legal vtotal is used, i.e. that "vtotal" is greater than or
+ * equal to vsync end.
+ *
+ * Always returns 0.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_set_vtotal(unsigned short vtotal)
+#else
+int gfx_set_vtotal(unsigned short vtotal)
+#endif
+{
+	unsigned long unlock, dcfg, vactive, vblank;
+
+    /* UNLOCK THE DISPLAY CONTROLLER REGISTERS */
+
+	unlock = READ_REG32(MDC_UNLOCK);
+	WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
+
+	/* READ THE CURRENT RC VALUES */
+
+    dcfg = READ_REG32 (MDC_DISPLAY_CFG);
+	vactive = READ_REG32 (MDC_V_ACTIVE_TIMING);
+	vblank  = READ_REG32 (MDC_V_BLANK_TIMING);
+
+	/* DISABLE TIMING REGISTER UPDATES */
+
+	WRITE_REG32 (MDC_DISPLAY_CFG, dcfg & ~(unsigned long)MDC_DCFG_TRUP);
+
+	/* WRITE NEW TIMING VALUES */
+
+	WRITE_REG32 (MDC_V_ACTIVE_TIMING, (vactive & MDC_VAT_VA_MASK)  | (unsigned long)(vtotal - 1) << 16);
+	WRITE_REG32 (MDC_V_BLANK_TIMING,  (vblank  & MDC_VBT_VBS_MASK) | (unsigned long)(vtotal - 1) << 16);
+
+	/* RESTORE OLD RC VALUES */
+
+	WRITE_REG32 (MDC_DISPLAY_CFG, dcfg);
+	WRITE_REG32 (MDC_UNLOCK, unlock);
+
+	return (0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_pitch
+ *
+ * This routine sets the pitch of the frame buffer to the specified value.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_display_pitch(unsigned short pitch)
+#else
+void gfx_set_display_pitch(unsigned short pitch)
+#endif
+{		
+	unsigned long value = 0;
+	unsigned long lock = READ_REG32(MDC_UNLOCK);
+	
+	value = READ_REG32(MDC_GFX_PITCH) & 0xFFFF0000;
+	value |= (pitch >> 3);
+	WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32(MDC_GFX_PITCH, value);
+
+	/* SET RENDERING PITCHES TO MATCH */
+
+	gfx_reset_pitch(pitch);
+
+	/* SET THE FRAME DIRTY MODE                  */
+	/* Non-standard pitches, i.e. pitches that   */
+	/* are not 1K, 2K or 4K must mark the entire */
+	/* frame as dirty when writing to the frame  */
+	/* buffer.                                   */
+
+	value = READ_REG32 (MDC_GENERAL_CFG);
+
+	if (pitch == 1024 || pitch == 2048 || pitch == 4096 || pitch == 8192)
+		value &= ~(unsigned long)(MDC_GCFG_FDTY);
+	else
+		value |=  (unsigned long)(MDC_GCFG_FDTY);
+
+	WRITE_REG32 (MDC_GENERAL_CFG, value);
+	WRITE_REG32(MDC_UNLOCK, lock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_offset
+ *
+ * This routine sets the start address of the frame buffer.  It is 
+ * typically used to pan across a virtual desktop (frame buffer larger than 
+ * the displayed screen) or to flip the display between multiple buffers.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_display_offset(unsigned long offset)
+#else
+void gfx_set_display_offset(unsigned long offset)
+#endif
+{
+	/* UPDATE FRAME BUFFER OFFSET */
+	unsigned long lock;
+	lock = READ_REG32(MDC_UNLOCK);
+	WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
+
+	
+	/* START ADDRESS EFFECTS DISPLAY COMPRESSION */
+	/* Disable compression for non-zero start addresss values.            */
+	/* Enable compression if offset is zero and comression is intended to */
+	/* be enabled from a previous call to "gfx_set_compression_enable".   */
+	/* Compression should be disabled BEFORE the offset is changed        */
+	/* and enabled AFTER the offset is changed.                           */
+	
+	if (offset == 0)
+	{
+		WRITE_REG32(MDC_FB_ST_OFFSET, offset);
+		if (gfx_compression_enabled)
+		{
+			/* WAIT FOR THE OFFSET TO BE LATCHED */
+			gfx_wait_vertical_blank ();
+			gu2_enable_compression();
+		}
+	}
+	else
+	{
+		/* ONLY DISABLE COMPRESSION ONCE */
+
+		if (gfx_compression_active)
+			gu2_disable_compression();
+
+		WRITE_REG32(MDC_FB_ST_OFFSET, offset);
+	}
+
+	WRITE_REG32(MDC_UNLOCK, lock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_palette_entry
+ *
+ * This routine sets an palette entry in the display controller.
+ * A 32-bit X:R:G:B value.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_set_display_palette_entry(unsigned long index, unsigned long palette)
+#else
+int gfx_set_display_palette_entry(unsigned long index, unsigned long palette)
+#endif
+{
+	if (index > 0xFF)
+		return GFX_STATUS_BAD_PARAMETER;
+
+	WRITE_REG32(MDC_PAL_ADDRESS, index);
+	WRITE_REG32(MDC_PAL_DATA, palette);
+
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_palette
+ *
+ * This routine sets the entire palette in the display controller.
+ * A pointer is provided to a 256 entry table of 32-bit X:R:G:B values.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_set_display_palette(unsigned long *palette)
+#else
+int gfx_set_display_palette(unsigned long *palette)
+#endif
+{
+	unsigned long i;
+	WRITE_REG32(MDC_PAL_ADDRESS, 0);
+	
+	if (palette)
+	{
+		for (i = 0; i < 256; i++)
+		{
+		    WRITE_REG32(MDC_PAL_DATA, palette[i]);
+		}
+	}
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_cursor_enable
+ *
+ * This routine enables or disables the hardware cursor.  
+ *
+ * WARNING: The cursor start offset must be set by setting the cursor 
+ * position before calling this routine to assure that memory reads do not
+ * go past the end of graphics memory (this can hang GXm).
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_cursor_enable(int enable)
+#else
+void gfx_set_cursor_enable(int enable)
+#endif
+{
+    unsigned long unlock, gcfg;
+	
+	/* SET OR CLEAR CURSOR ENABLE BIT */
+
+	unlock = READ_REG32(MDC_UNLOCK);
+	gcfg   = READ_REG32(MDC_GENERAL_CFG);
+	if (enable) gcfg |=   MDC_GCFG_CURE;
+	else        gcfg &= ~(MDC_GCFG_CURE);
+
+	/* WRITE NEW REGISTER VALUE */
+
+	WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32(MDC_GENERAL_CFG, gcfg);
+	WRITE_REG32(MDC_UNLOCK, unlock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_cursor_colors
+ *
+ * This routine sets the colors of the hardware cursor.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor)
+#else
+void gfx_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor)
+#endif
+{
+	/* SET CURSOR COLORS */
+
+	WRITE_REG32(MDC_PAL_ADDRESS, 0x100);
+	WRITE_REG32(MDC_PAL_DATA, bkcolor);
+	WRITE_REG32(MDC_PAL_DATA, fgcolor);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_cursor_position
+ *
+ * This routine sets the position of the hardware cusror.  The starting
+ * offset of the cursor buffer must be specified so that the routine can 
+ * properly clip scanlines if the cursor is off the top of the screen.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_cursor_position(unsigned long memoffset, 
+	unsigned short xpos, unsigned short ypos, 
+	unsigned short xhotspot, unsigned short yhotspot)
+#else
+void gfx_set_cursor_position(unsigned long memoffset, 
+	unsigned short xpos, unsigned short ypos, 
+	unsigned short xhotspot, unsigned short yhotspot)
+#endif
+{
+    unsigned long unlock;
+
+	short x = (short) xpos - (short) xhotspot;
+	short y = (short) ypos - (short) yhotspot;
+	short xoffset = 0;
+	short yoffset = 0;
+	if (x < -63) return;
+	if (y < -63) return;
+	
+	if (PanelEnable) 
+	{
+		if (( ModeWidth > PanelWidth) || (ModeHeight > PanelHeight)) 
+		{ 
+			gfx_enable_panning(xpos, ypos);
+			x = x - (unsigned short)panelLeft;
+			y = y - (unsigned short)panelTop;
+		}
+	}
+
+	/* ADJUST OFFSETS */
+	/* Cursor movement and panning work as follows:  The cursor position   */
+	/* refers to where the hotspot of the cursor is located.  However, for */
+	/* non-zero hotspots, the cursor buffer actually begins before the     */
+	/* specified position.                                                 */
+
+	if (x < 0) { xoffset = -x; x = 0; }
+	if (y < 0) { yoffset = -y; y = 0; }
+	memoffset += (unsigned long) yoffset << 4;
+
+	/* SET CURSOR POSITION */
+
+	unlock = READ_REG32(MDC_UNLOCK);
+	WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32(MDC_CURS_ST_OFFSET, memoffset);
+	WRITE_REG32(MDC_CURSOR_X, (unsigned long) x |
+		(((unsigned long) xoffset) << 11));
+	WRITE_REG32(MDC_CURSOR_Y, (unsigned long) y | 
+		(((unsigned long) yoffset) << 11));
+	WRITE_REG32(MDC_UNLOCK, unlock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_cursor_shape32
+ *
+ * This routine loads 32x32 cursor data into the cursor buffer in graphics memory.
+ * As the Redcloud cursor is actually 64x64, we must pad the outside of the 
+ * cursor data with transparent pixels.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_cursor_shape32(unsigned long memoffset, 
+	unsigned long *andmask, unsigned long *xormask)
+#else
+void gfx_set_cursor_shape32(unsigned long memoffset, 
+	unsigned long *andmask, unsigned long *xormask)
+#endif
+{
+	int i;
+
+	for (i = 0; i < 32; i++)
+	{
+		/* EVEN QWORDS CONTAIN THE AND MASK */
+
+		WRITE_FB32 (memoffset, 0xFFFFFFFF);
+		WRITE_FB32 (memoffset + 4, andmask[i]);
+
+		/* ODD QWORDS CONTAIN THE XOR MASK  */
+
+		WRITE_FB32 (memoffset + 8, 0x00000000);
+		WRITE_FB32 (memoffset + 12, xormask[i]);
+
+		memoffset += 16;
+	}
+
+	/* FILL THE LOWER HALF OF THE BUFFER WITH TRANSPARENT PIXELS */
+
+	for (i = 0; i < 32; i++)
+	{
+		WRITE_FB32 (memoffset,      0xFFFFFFFF);
+		WRITE_FB32 (memoffset + 4,  0xFFFFFFFF);
+		WRITE_FB32 (memoffset + 8,  0x00000000);
+		WRITE_FB32 (memoffset + 12, 0x00000000);
+
+		memoffset += 16;
+	}
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_cursor_shape64
+ *
+ * This routine loads 64x64 cursor data into the cursor buffer in graphics memory.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_cursor_shape64(unsigned long memoffset, 
+	unsigned long *andmask, unsigned long *xormask)
+#else
+void gfx_set_cursor_shape64(unsigned long memoffset, 
+	unsigned long *andmask, unsigned long *xormask)
+#endif
+{	
+	int i;
+
+	for (i = 0; i < 128; i += 2)
+	{
+		/* EVEN QWORDS CONTAIN THE AND MASK */
+		/* We invert the dwords to prevent the calling            */
+		/* application from having to think in terms of Qwords.   */
+		/* The hardware data order is actually 63:0, or 31:0 of   */
+		/* the second dword followed by 31:0 of the first dword.  */
+		
+		WRITE_FB32 (memoffset, andmask[i + 1]);
+		WRITE_FB32 (memoffset + 4, andmask[i]);
+
+		/* ODD QWORDS CONTAIN THE XOR MASK  */
+
+		WRITE_FB32 (memoffset + 8, xormask[i + 1]);
+		WRITE_FB32 (memoffset + 12, xormask[i]);
+
+		memoffset += 16;
+	}
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_icon_enable
+ *
+ * This routine enables or disables the hardware icon.  The icon position
+ * and colors should be programmed prior to calling this routine for the
+ * first time.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_icon_enable(int enable)
+#else
+void gfx_set_icon_enable(int enable)
+#endif
+{	
+    unsigned long unlock, gcfg;
+	
+	/* SET OR CLEAR ICON ENABLE BIT */
+
+	unlock = READ_REG32(MDC_UNLOCK);
+	gcfg   = READ_REG32(MDC_GENERAL_CFG);
+	if (enable) gcfg |=   MDC_GCFG_ICNE;
+	else        gcfg &= ~(MDC_GCFG_ICNE);
+
+	/* WRITE NEW REGISTER VALUE */
+
+	WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32(MDC_GENERAL_CFG, gcfg);
+	WRITE_REG32(MDC_UNLOCK, unlock);	
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_icon_colors
+ *
+ * This routine sets the three icon colors.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_icon_colors(unsigned long color0, unsigned long color1, unsigned long color2)
+#else
+void gfx_set_icon_colors(unsigned long color0, unsigned long color1, unsigned long color2)
+#endif
+{
+	/* ICON COLORS LOCATED AT PALETTE INDEXES 102-104h */
+	
+    WRITE_REG32 (MDC_PAL_ADDRESS, 0x102);
+	
+	WRITE_REG32 (MDC_PAL_DATA, color0);
+	WRITE_REG32 (MDC_PAL_DATA, color1);
+	WRITE_REG32 (MDC_PAL_DATA, color2);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_icon_position
+ *
+ * This routine sets the starting X coordinate for the hardware icon and the 
+ * memory offset for the icon buffer.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_icon_position(unsigned long memoffset, unsigned short xpos)
+#else
+void gfx_set_icon_position(unsigned long memoffset, unsigned short xpos)
+#endif
+{
+	unsigned long lock = READ_REG32 (MDC_UNLOCK);
+
+	WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE);
+
+	/* PROGRAM THE MEMORY OFFSET */
+
+	WRITE_REG32 (MDC_ICON_ST_OFFSET, memoffset & 0x0FFFFFFF);
+
+	/* PROGRAM THE XCOORDINATE */
+
+	WRITE_REG32 (MDC_ICON_X, (unsigned long)(xpos & 0x07FF));
+
+	WRITE_REG32 (MDC_UNLOCK, lock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_icon_shape64
+ *
+ * This routine initializes the icon buffer according to the current mode.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_icon_shape64(unsigned long memoffset, unsigned long *andmask, unsigned long *xormask, unsigned int lines)
+#else
+void gfx_set_icon_shape64(unsigned long memoffset, unsigned long *andmask, unsigned long *xormask, unsigned int lines)
+#endif
+{
+	unsigned short i, height;
+
+	height = lines << 1;
+	
+	for (i = 0; i < height; i += 2)
+	{
+		/* EVEN QWORDS CONTAIN THE AND MASK     */
+		/* Swap dwords to hide qword constraint */
+
+		WRITE_FB32 (memoffset, andmask[i + 1]);
+		WRITE_FB32 (memoffset + 4, andmask[i]);
+
+		/* ODD QWORDS CONTAIN THE XOR MASK */
+
+		WRITE_FB32 (memoffset + 8,  xormask[i + 1]);
+		WRITE_FB32 (memoffset + 12, xormask[i]);
+
+		memoffset += 16;
+	}
+}
+
+/*---------------------------------------------------------------------------
+ * gu2_enable_compression
+ *
+ * This is a private routine to this module (not exposed in the Durango API).
+ * It enables display compression.
+ *---------------------------------------------------------------------------
+ */
+void gu2_enable_compression(void)
+{
+	unsigned long unlock, gcfg, temp;
+
+	/* DO NOT ENABLE IF START ADDRESS IS NOT ZERO */
+
+	if (READ_REG32(MDC_FB_ST_OFFSET) & 0x0FFFFFFF)
+		return;
+	
+	/* SET GLOBAL INDICATOR */
+
+	gfx_compression_active = 1;
+
+	/* CLEAR DIRTY/VALID BITS IN MEMORY CONTROLLER */
+	/* Software is required to do this before enabling compression.   */
+	/* Don't want controller to think that old lines are still valid. */
+	/* Writing a 1 to bit 0 of the DV Control register will force the */
+	/* hardware to clear all the valid bits.                          */
+
+	temp = READ_REG32 (MDC_DV_CTL);
+	WRITE_REG32 (MDC_DV_CTL, temp | 0x00000001);
+
+	/* TURN ON COMPRESSION CONTROL BITS */
+
+	unlock = READ_REG32 (MDC_UNLOCK);
+	gcfg   = READ_REG32 (MDC_GENERAL_CFG);
+	gcfg  |= MDC_GCFG_CMPE | MDC_GCFG_DECE;
+	WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32 (MDC_GENERAL_CFG, gcfg);
+	WRITE_REG32 (MDC_UNLOCK, unlock);
+}
+
+/*---------------------------------------------------------------------------
+ * gu2_disable_compression
+ *
+ * This is a private routine to this module (not exposed in the Durango API).
+ * It disables display compression.
+ *---------------------------------------------------------------------------
+ */
+void gu2_disable_compression(void)
+{
+	unsigned long unlock, gcfg;
+
+	/* SET GLOBAL INDICATOR */
+
+	gfx_compression_active = 0;
+
+	/* TURN OFF COMPRESSION CONTROL BITS */
+
+	unlock = READ_REG32(MDC_UNLOCK);
+	gcfg = READ_REG32(MDC_GENERAL_CFG);
+	gcfg &= ~(MDC_GCFG_CMPE | MDC_GCFG_DECE);
+	WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32 (MDC_GENERAL_CFG, gcfg);
+	WRITE_REG32 (MDC_UNLOCK, unlock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_compression_enable
+ *
+ * This routine enables or disables display compression.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_set_compression_enable(int enable)
+#else
+int gfx_set_compression_enable(int enable)
+#endif
+{
+	/* SET GLOBAL VARIABLE FOR INDENDED STATE */
+	/* Compression can only be enabled for non-zero start address values. */
+	/* Keep state to enable compression on start address changes. */
+
+	gfx_compression_enabled = enable;
+	if (enable) gu2_enable_compression();
+	else gu2_disable_compression();
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_compression_offset
+ *
+ * This routine sets the base offset for the compression buffer.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_set_compression_offset(unsigned long offset)
+#else
+int gfx_set_compression_offset(unsigned long offset)
+#endif
+{
+	unsigned long lock;
+	
+	/* MUST BE 16-BYTE ALIGNED FOR REDCLOUD */
+
+	if (offset & 0x0F) return(1);
+
+	/* SET REGISTER VALUE */
+
+	lock = READ_REG32(MDC_UNLOCK);
+	WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32(MDC_CB_ST_OFFSET, offset & 0x0FFFFFFF);
+	WRITE_REG32(MDC_UNLOCK, lock);
+
+	return (0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_compression_pitch
+ *
+ * This routine sets the pitch, in bytes, of the compression buffer. 
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_set_compression_pitch(unsigned short pitch)
+#else
+int gfx_set_compression_pitch(unsigned short pitch)
+#endif
+{
+	unsigned long lock, line_delta;
+	
+	lock = READ_REG32(MDC_UNLOCK);
+
+	/* SET REGISTER VALUE */
+
+	line_delta = READ_REG32(MDC_GFX_PITCH) & 0x0000FFFF;
+	line_delta |= (((unsigned long)pitch << 13) & 0xFFFF0000);
+	WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32(MDC_GFX_PITCH, line_delta);
+	WRITE_REG32(MDC_UNLOCK, lock);
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_compression_size
+ *
+ * This routine sets the line size of the compression buffer, which is the
+ * maximum number of bytes allowed to store a compressed line.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_set_compression_size(unsigned short size)
+#else
+int gfx_set_compression_size(unsigned short size)
+#endif
+{
+	unsigned long lock, buf_size;
+
+	/* SUBTRACT 32 FROM SIZE                          */
+	/* The display controller will actually write     */
+	/* 4 extra QWords.  So, if we assume that "size"  */
+	/* refers to the allocated size, we must subtract */
+	/* 32 bytes.                                      */
+
+	size -= 32;
+	
+	/* SET REGISTER VALUE */
+
+	lock = READ_REG32(MDC_UNLOCK);
+	buf_size = READ_REG32(MDC_LINE_SIZE) & 0xFF80FFFF;
+	buf_size |= ((((unsigned long)size >> 3) + 1) & 0x7F) << 16;
+	WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32(MDC_LINE_SIZE, buf_size);
+	WRITE_REG32(MDC_UNLOCK, lock);
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_format (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_format".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_display_video_format(unsigned long format)
+#else
+void gfx_set_display_video_format(unsigned long format)
+#endif
+{
+	unsigned long gcfg, lock;
+
+	lock = READ_REG32 (MDC_UNLOCK);
+	gcfg = READ_REG32 (MDC_GENERAL_CFG);
+
+   	switch (format)
+	{
+		case VIDEO_FORMAT_Y0Y1Y2Y3:
+		case VIDEO_FORMAT_Y3Y2Y1Y0:
+		case VIDEO_FORMAT_Y1Y0Y3Y2:
+		case VIDEO_FORMAT_Y1Y2Y3Y0:
+
+			gcfg |= MDC_GCFG_YUVM;
+			break;
+
+		default:
+
+			gcfg &= ~MDC_GCFG_YUVM;
+			break;
+	}
+
+	WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32 (MDC_GENERAL_CFG, gcfg);
+	WRITE_REG32 (MDC_UNLOCK, lock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_enable (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_enable".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_display_video_enable(int enable)
+#else
+void gfx_set_display_video_enable(int enable)
+#endif
+{
+   	unsigned long lock, gcfg, dcfg;
+
+	/* READ CURRENT VALUES */
+
+	lock = READ_REG32 (MDC_UNLOCK);
+	gcfg = READ_REG32 (MDC_GENERAL_CFG);
+	dcfg = READ_REG32 (MDC_DISPLAY_CFG);
+
+	/* SET OR CLEAR VIDEO ENABLE IN GENERAL_CFG */
+
+	if (enable) gcfg |=  MDC_GCFG_VIDE;
+	else        gcfg &= ~MDC_GCFG_VIDE;
+
+	/* WRITE REGISTER */
+
+	WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32 (MDC_GENERAL_CFG, gcfg);
+	WRITE_REG32 (MDC_UNLOCK, lock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_size (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_size".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_display_video_size(unsigned short width, unsigned short height)
+#else
+void gfx_set_display_video_size(unsigned short width, unsigned short height)
+#endif
+{
+	unsigned long lock, value, yuv_420;
+
+	/* READ CURRENT VALUES */
+
+	lock     = READ_REG32 (MDC_UNLOCK);
+	value    = READ_REG32 (MDC_LINE_SIZE) & 0x00FFFFFF;
+	yuv_420  = READ_REG32 (MDC_GENERAL_CFG) & MDC_GCFG_YUVM;
+		
+	/* LINE WIDTH IS 1/4 FOR 4:2:0 VIDEO */
+	/* All data must be 32-byte aligned. */
+	
+	if (yuv_420)
+	{
+		width >>= 1;
+		width = (width + 7) & 0xFFF8;
+	}
+	else
+	{
+	    width <<= 1;
+		width = (width + 31) & 0xFFE0;
+	}
+	
+	/* ONLY THE LINE SIZE IS PROGRAMMED IN THE DISPLAY CONTROLLER */
+
+	value |= ((unsigned long)width << 21);
+	
+	/* WRITE THE REGISTER */
+
+	WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32 (MDC_LINE_SIZE, value);
+	WRITE_REG32 (MDC_UNLOCK, lock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_offset (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_offset".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_display_video_offset(unsigned long offset)
+#else
+void gfx_set_display_video_offset(unsigned long offset)
+#endif
+{
+	unsigned long lock;
+	
+	lock = READ_REG32(MDC_UNLOCK);
+	WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	offset &= 0x0FFFFFF0;
+	WRITE_REG32(MDC_VID_Y_ST_OFFSET, offset);
+	WRITE_REG32(MDC_UNLOCK, lock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_yuv_offsets (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by gfx_set_video_yuv_offsets.  It abstracts the version
+ * of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_display_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, 
+									   unsigned long voffset)
+#else
+void gfx_set_display_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, 
+									   unsigned long voffset)
+#endif
+{
+	unsigned long lock;
+	
+	lock = READ_REG32(MDC_UNLOCK);
+	
+	yoffset &= 0x0FFFFFF0;
+	uoffset &= 0x0FFFFFF8;
+	voffset &= 0x0FFFFFF8;
+
+	WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32(MDC_VID_Y_ST_OFFSET, yoffset);
+	WRITE_REG32(MDC_VID_U_ST_OFFSET, uoffset);
+	WRITE_REG32(MDC_VID_V_ST_OFFSET, voffset);
+	WRITE_REG32(MDC_UNLOCK, lock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_yuv_pitch (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by gfx_set_video_yuv_pitch.  It abstracts the version
+ * of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_display_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch)
+#else
+void gfx_set_display_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch)
+#endif
+{
+	unsigned long lock, pitch;
+	
+	lock = READ_REG32(MDC_UNLOCK);
+	
+	pitch = ((uvpitch << 13) & 0xFFFF0000) | ((ypitch >> 3) & 0xFFFF);
+
+	WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32(MDC_VID_YUV_PITCH, pitch);
+	WRITE_REG32(MDC_UNLOCK, lock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_downscale (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by gfx_set_video_vertical_downscale.  It abstracts the version
+ * of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_display_video_downscale (unsigned short srch, unsigned short dsth)
+#else
+void gfx_set_display_video_downscale (unsigned short srch, unsigned short dsth)
+#endif
+{
+	unsigned long lock, delta;
+	
+	lock = READ_REG32 (MDC_UNLOCK);
+
+	/* CLIP SCALING LIMITS */
+	/* Upscaling is performed in a separate function. */
+	/* Maximum scale ratio is 1/2.                    */
+
+	if (dsth > srch || dsth <= (srch >> 1))
+		delta = 0;
+	else
+		delta = (((unsigned long)srch << 14) / (unsigned long)dsth) << 18;
+
+	WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32 (MDC_VID_DS_DELTA, delta);
+	WRITE_REG32 (MDC_UNLOCK, lock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_downscale_enable (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_vertical_downscale_enable".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_set_display_video_vertical_downscale_enable(int enable) 
+#else
+void gfx_set_display_video_vertical_downscale_enable(int enable) 
+#endif
+{
+	unsigned long gcfg, unlock;
+
+	unlock = READ_REG32 (MDC_UNLOCK);
+	gcfg   = READ_REG32 (MDC_GENERAL_CFG);
+
+	if (enable) gcfg |=  MDC_GCFG_VDSE;
+	else        gcfg &= ~MDC_GCFG_VDSE;
+
+	WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE);
+	WRITE_REG32 (MDC_GENERAL_CFG, gcfg);
+	WRITE_REG32 (MDC_UNLOCK, unlock);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_test_timing_active
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_test_timing_active(void)
+#else
+int gfx_test_timing_active(void)
+#endif
+{
+	if (READ_REG32 (MDC_DISPLAY_CFG) & MDC_DCFG_TGEN)
+		return(1);
+	else return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_test_vertical_active
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_test_vertical_active(void)
+#else
+int gfx_test_vertical_active(void)
+#endif
+{
+	if (READ_REG32 (MDC_LINE_CNT_STATUS) & MDC_LNCNT_VNA)
+		return(0);
+
+	return(1);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_wait_vertical_blank
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_wait_vertical_blank(void)
+#else
+int gfx_wait_vertical_blank(void)
+#endif
+{
+	if (gfx_test_timing_active())
+	{
+		while(!gfx_test_vertical_active());
+		while(gfx_test_vertical_active());
+	}
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_enable_panning 
+ *
+ * This routine  enables the panning when the Mode is bigger than the panel
+ * size.
+ *---------------------------------------------------------------------------
+ */
+
+#if GFX_DISPLAY_DYNAMIC
+void gu2_enable_panning(int x, int y)
+#else
+void gfx_enable_panning(int x, int y) 
+#endif
+{
+    unsigned long modeBytesPerPixel;
+    unsigned long modeBytesPerScanline = 0;
+    unsigned long startAddress = 0;
+        
+    modeBytesPerPixel    = (gbpp + 7)/8;
+	modeBytesPerScanline = (READ_REG32 (MDC_GFX_PITCH) & 0x0000FFFF) << 3;
+
+	/* TEST FOR NO-WORK */
+
+	if (x >= DeltaX && x < ((int)PanelWidth  + DeltaX) && 
+		y >= DeltaY && y < ((int)PanelHeight + DeltaY))
+		return;
+
+	/* ADJUST PANNING VARIABLES WHEN CURSOR EXCEEDS BOUNDARY       */
+	/* Test the boundary conditions for each coordinate and update */
+	/* all variables and the starting offset accordingly.          */
+	
+	if (x < DeltaX)
+		DeltaX = x;
+
+	else if (x >= (DeltaX + (int)PanelWidth))
+		DeltaX = x - (int)PanelWidth + 1;
+
+	if (y < DeltaY)
+		DeltaY = y;
+
+	else if (y >= (DeltaY + (int)PanelHeight))
+		DeltaY = y - (int)PanelHeight + 1; 
+
+	/* CALCULATE THE START OFFSET */
+
+	startAddress = (DeltaX * modeBytesPerPixel) + (DeltaY * modeBytesPerScanline);
+	
+	gfx_set_display_offset(startAddress);
+
+	/* SET PANEL COORDINATES                    */
+	/* Panel's x position must be DWORD aligned */
+
+    panelTop  = DeltaY;
+	panelLeft = DeltaX * modeBytesPerPixel;
+
+	if (panelLeft & 3)
+		panelLeft = (panelLeft & 0xFFFFFFFC) + 4;
+
+	panelLeft /= modeBytesPerPixel;
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_fixed_timings
+ *---------------------------------------------------------------------------
+ */
+
+#if GFX_DISPLAY_DYNAMIC
+int gu2_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp)
+#else
+int gfx_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height,  unsigned short bpp)
+#endif
+{
+	unsigned int mode;
+
+	ModeWidth   = width;
+	ModeHeight  = height;
+	PanelWidth  = (unsigned short)panelResX;
+	PanelHeight = (unsigned short)panelResY;
+	PanelEnable = 1;
+
+	/* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */
+	for (mode = 0; mode < NUM_FIXED_TIMINGS_MODES; mode++) {
+		if ((FixedParams[mode].xres == width) &&
+			(FixedParams[mode].yres == height) &&
+			(FixedParams[mode].panelresx == panelResX) &&
+			(FixedParams[mode].panelresy == panelResY)) {
+
+			/* SET THE 92xx FOR THE SELECTED MODE */
+			FIXEDTIMINGS *fmode = &FixedParams[mode];
+
+			gfx_set_display_timings(bpp, 3, fmode->hactive,fmode->hblankstart, fmode->hsyncstart, fmode->hsyncend,
+				fmode->hblankend, fmode->htotal, fmode->vactive, fmode->vblankstart, 
+				fmode->vsyncstart,	fmode->vsyncend, fmode->vblankend, fmode->vtotal, fmode->frequency);  										
+	
+			return(1);
+			} /* end if() */
+		} /* end for() */
+
+	return(-1);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_panel_present
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp)
+#else
+int gfx_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp)
+#endif
+{
+	/* SET VALID BPP         */
+	/* 16BPP is the default. */
+
+	if (bpp != 8 && bpp != 12 && bpp != 15 && bpp != 16 && bpp != 32)
+		bpp = 16;
+
+	/* RECORD PANEL PARAMETERS */
+	/* This routine does not touch any panel timings.  It is used when custom panel */
+	/* settings are set up in advance by the BIOS or an application, but the        */
+	/* application still requires access to other panel functionality provided by   */
+	/* Durango (i.e. panning).                                                      */
+
+	ModeWidth   = width;
+	ModeHeight  = height;
+	PanelWidth  = (unsigned short)panelResX;
+	PanelHeight = (unsigned short)panelResY;
+	PanelEnable = 1;
+	gbpp        = bpp;
+
+	/* PROGRAM THE BPP IN THE DISPLAY CONTROLLER */
+
+	gfx_set_display_bpp (bpp);
+
+	return(GFX_STATUS_OK);
+}
+
+/* THE FOLLOWING READ ROUTINES ARE ALWAYS INCLUDED: */
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_pitch
+ *
+ * This routine returns the current pitch of the frame buffer, in bytes.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_display_pitch(void)
+#else
+unsigned short gfx_get_display_pitch(void)
+#endif
+{	
+	return ((unsigned short)(READ_REG32 (MDC_GFX_PITCH) & 0x0000FFFF) << 3);
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_mode_frequency_supported
+ *
+ * This routine examines if the requested mode with pixel frequency is supported.
+ *
+ * Returns >0 if successful , <0 if freq. could not be found and matched.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency)
+#else
+int gfx_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency)
+#endif
+{
+	unsigned int index;
+	unsigned long value;
+	unsigned long bpp_flag = 0;
+
+	switch (bpp)
+	{
+	    case 8:  bpp_flag = GFX_MODE_8BPP;  break;
+		case 12: bpp_flag = GFX_MODE_12BPP; break;
+		case 15: bpp_flag = GFX_MODE_15BPP; break;
+		case 16: bpp_flag = GFX_MODE_16BPP; break;
+		case 32: bpp_flag = GFX_MODE_24BPP; break;
+		default: bpp_flag = GFX_MODE_8BPP;  break;
+	}
+
+	for (index = 0; index < NUM_RC_DISPLAY_MODES; index++)
+	{
+		if ((DisplayParams[index].hactive == (unsigned int)xres) &&
+			(DisplayParams[index].vactive == (unsigned int)yres) &&
+			(DisplayParams[index].flags & bpp_flag) &&
+			(DisplayParams[index].frequency == frequency))
+		{
+			int hz=0;
+			value = DisplayParams[index].flags;
+
+			if (value & GFX_MODE_56HZ)      hz = 56;
+			else if (value & GFX_MODE_60HZ) hz = 60;
+			else if (value & GFX_MODE_70HZ) hz = 70;
+			else if (value & GFX_MODE_72HZ) hz = 72;
+			else if (value & GFX_MODE_75HZ) hz = 75;
+			else if (value & GFX_MODE_85HZ) hz = 85;
+			return(hz);
+		}
+	}
+
+	return(-1);
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_refreshrate_from_frequency
+ *
+ * This routine maps the frequency to close match refresh rate
+ *
+ * Returns .
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency)
+#else
+int gfx_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency)
+#endif
+{
+	unsigned int index, closematch=0;
+	unsigned long value;
+	unsigned long bpp_flag = 0;
+	long min, diff;
+	
+	*hz = 60;
+
+	switch (bpp)
+	{
+	    case 8:  bpp_flag = GFX_MODE_8BPP;  break;
+		case 12: bpp_flag = GFX_MODE_12BPP; break;
+		case 15: bpp_flag = GFX_MODE_15BPP; break;
+		case 16: bpp_flag = GFX_MODE_16BPP; break;
+		case 32: bpp_flag = GFX_MODE_24BPP; break;
+		default: bpp_flag = GFX_MODE_8BPP;  break;
+	}
+
+	/* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */
+	/* Search the table for the closest frequency (16.16 format). */
+
+	min = 0x7fffffff;
+	for (index = 0; index < NUM_RC_DISPLAY_MODES; index++)
+	{
+		if ((DisplayParams[index].htotal == (unsigned int)xres) &&
+			(DisplayParams[index].vtotal == (unsigned int)yres) &&
+			(DisplayParams[index].flags & bpp_flag)) 
+		{
+			diff = (long)frequency - (long)DisplayParams[index].frequency;
+			if(diff < 0) diff = -diff;
+			
+			if (diff < min)
+			{
+				min = diff; 
+				closematch = index;
+			} 
+		}
+	}
+	
+	value = DisplayParams[closematch].flags;
+
+	if      (value & GFX_MODE_56HZ) *hz = 56;
+	else if (value & GFX_MODE_60HZ) *hz = 60;
+	else if (value & GFX_MODE_70HZ) *hz = 70;
+	else if (value & GFX_MODE_72HZ) *hz = 72;
+	else if (value & GFX_MODE_75HZ) *hz = 75;
+	else if (value & GFX_MODE_85HZ) *hz = 85;
+
+	return(1);
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_refreshrate_from_mode
+ *
+ * This routine is identical to the gfx_get_refreshrate_from_frequency,
+ * except that the active timing values are compared instead of the total
+ * values.  Some modes (such as 70Hz and 72Hz) may be confused in this routine.
+ *
+ * Returns .
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency)
+#else
+int gfx_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency)
+#endif
+{
+	unsigned int index, closematch=0;
+	unsigned long value;
+	unsigned long bpp_flag = 0;
+	long min, diff;
+	
+	*hz = 60;
+
+	switch (bpp)
+	{
+	    case 8:  bpp_flag = GFX_MODE_8BPP;  break;
+		case 12: bpp_flag = GFX_MODE_12BPP; break;
+		case 15: bpp_flag = GFX_MODE_15BPP; break;
+		case 16: bpp_flag = GFX_MODE_16BPP; break;
+		case 32: bpp_flag = GFX_MODE_24BPP; break;
+		default: bpp_flag = GFX_MODE_8BPP;  break;
+	}
+
+	/* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */
+	/* Search the table for the closest frequency (16.16 format). */
+
+	min = 0x7fffffff;
+	for (index = 0; index < NUM_RC_DISPLAY_MODES; index++)
+	{
+		if ((DisplayParams[index].hactive == (unsigned int)xres) &&
+			(DisplayParams[index].vactive == (unsigned int)yres) &&
+			(DisplayParams[index].flags & bpp_flag)) 
+		{
+			diff = (long)frequency - (long)DisplayParams[index].frequency;
+			if(diff < 0) diff = -diff;
+			
+			if (diff < min)
+			{
+				min = diff; 
+				closematch = index;
+			} 
+		}
+	}
+	
+	value = DisplayParams[closematch].flags;
+
+	if      (value & GFX_MODE_56HZ) *hz = 56;
+	else if (value & GFX_MODE_60HZ) *hz = 60;
+	else if (value & GFX_MODE_70HZ) *hz = 70;
+	else if (value & GFX_MODE_72HZ) *hz = 72;
+	else if (value & GFX_MODE_75HZ) *hz = 75;
+	else if (value & GFX_MODE_85HZ) *hz = 85;
+
+	return(1);
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_get_frequency_from_refreshrate
+ *
+ * This routine maps the refresh rate to the closest matching PLL frequency.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency)
+#else
+int gfx_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency)
+#endif
+{
+	unsigned int index;
+	int retval = -1;
+	unsigned long hz_flag  = 0;
+	unsigned long bpp_flag = 0;
+	
+	*frequency = 0;
+
+	if      (hz == 56) hz_flag = GFX_MODE_56HZ;
+	if      (hz == 60) hz_flag = GFX_MODE_60HZ;
+	else if (hz == 70) hz_flag = GFX_MODE_70HZ;
+	else if (hz == 72) hz_flag = GFX_MODE_72HZ;
+	else if (hz == 75) hz_flag = GFX_MODE_75HZ;
+	else if (hz == 85) hz_flag = GFX_MODE_85HZ;
+
+	switch (bpp)
+	{
+	    case 8:  bpp_flag = GFX_MODE_8BPP;  break;
+		case 12: bpp_flag = GFX_MODE_12BPP; break;
+		case 15: bpp_flag = GFX_MODE_15BPP; break;
+		case 16: bpp_flag = GFX_MODE_16BPP; break;
+		case 32: bpp_flag = GFX_MODE_24BPP; break;
+		default: bpp_flag = GFX_MODE_8BPP;  break;
+	}
+
+	/* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */
+	/* Search the table for the closest frequency (16.16 format). */
+
+	for (index = 0; index < NUM_RC_DISPLAY_MODES; index++)
+	{
+		if ((DisplayParams[index].hactive == (unsigned short)xres) &&
+			(DisplayParams[index].vactive == (unsigned short)yres) &&
+			(DisplayParams[index].flags & bpp_flag)  &&
+			(DisplayParams[index].flags & hz_flag)) 
+		{
+			*frequency = DisplayParams[index].frequency;
+			retval = 1;
+		}
+	}
+	return retval;
+}
+
+
+/*---------------------------------------------------------------------------
+ * gfx_get_max_supported_pixel_clock
+ *
+ * This routine returns the maximum recommended speed for the pixel clock.  The 
+ * return value is an integer of the format xxxyyy, where xxx.yyy is the maximum
+ * floating point pixel clock speed.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_max_supported_pixel_clock (void)
+#else
+unsigned long gfx_get_max_supported_pixel_clock (void)
+#endif
+
+{
+    return 229500;
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_get_display_mode
+ *
+ * This routine gets the specified display mode.
+ *
+ * Returns >0 if successful and mode returned, <0 if mode could not be found.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_get_display_mode(int *xres, int *yres, int *bpp, int *hz)
+#else
+int gfx_get_display_mode(int *xres, int *yres, int *bpp, int *hz)
+#endif
+{
+	unsigned int mode=0;
+	unsigned long pll_freq = 0, bpp_flag = 0;
+
+	*xres    = gfx_get_hactive();
+	*yres    = gfx_get_vactive();
+	*bpp     = gfx_get_display_bpp();
+	pll_freq = gfx_get_clock_frequency();
+
+	/* SET BPP FLAGS TO LIMIT MODE SELECTION */
+
+	switch (*bpp)
+	{
+	    case 8:  bpp_flag = GFX_MODE_8BPP;  break;
+		case 12: bpp_flag = GFX_MODE_12BPP; break;
+		case 15: bpp_flag = GFX_MODE_15BPP; break;
+		case 16: bpp_flag = GFX_MODE_16BPP; break;
+		case 32: bpp_flag = GFX_MODE_24BPP; break;
+		default: bpp_flag = GFX_MODE_8BPP;  break;
+	}
+
+	for (mode = 0; mode < NUM_RC_DISPLAY_MODES; mode++) {
+		if ((DisplayParams[mode].hactive == (unsigned int)*xres) &&
+			(DisplayParams[mode].vactive == (unsigned int)*yres) &&
+			(DisplayParams[mode].frequency == pll_freq) &&
+			(DisplayParams[mode].flags & bpp_flag)) {
+
+				pll_freq = DisplayParams[mode].flags;
+
+				if      (pll_freq & GFX_MODE_56HZ) *hz = 56;
+				else if (pll_freq & GFX_MODE_60HZ) *hz = 60;
+				else if (pll_freq & GFX_MODE_70HZ) *hz = 70;
+				else if (pll_freq & GFX_MODE_72HZ) *hz = 72;
+				else if (pll_freq & GFX_MODE_75HZ) *hz = 75;
+				else if (pll_freq & GFX_MODE_85HZ) *hz = 85;
+
+				return(1);
+			}
+		} 
+	return(-1);
+}
+
+/*----------------------------------------------------------------------------
+ * GFX_GET_DISPLAY_DETAILS
+ *
+ * This routine gets the specified display mode.
+ *
+ * Returns 1 if successful, 0 if mode could not be get.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_get_display_details(unsigned int mode, int *xres, int *yres, int *hz)
+#else
+int gfx_get_display_details(unsigned int mode, int *xres, int *yres, int *hz)
+#endif
+{
+	if(mode < NUM_RC_DISPLAY_MODES)
+	{
+		if(DisplayParams[mode].flags & GFX_MODE_56HZ)
+			*hz = 56;
+		else if(DisplayParams[mode].flags & GFX_MODE_60HZ)
+			*hz = 60;
+		else if(DisplayParams[mode].flags & GFX_MODE_70HZ)
+			*hz = 70;
+		else if(DisplayParams[mode].flags & GFX_MODE_72HZ)
+			*hz = 72;
+		else if(DisplayParams[mode].flags & GFX_MODE_75HZ)
+			*hz = 75;
+		else if(DisplayParams[mode].flags & GFX_MODE_85HZ)
+			*hz = 85;
+
+		*xres = DisplayParams[mode].hactive;
+		*yres = DisplayParams[mode].vactive;
+
+		if (DisplayParams[mode].flags & GFX_MODE_PIXEL_DOUBLE)
+			*xres >>= 1;
+		if (DisplayParams[mode].flags & GFX_MODE_LINE_DOUBLE)
+			*yres >>= 1;
+
+		return(1);
+	}
+	return(0);
+}
+
+/*----------------------------------------------------------------------------
+ * GFX_GET_DISPLAY_MODE_COUNT
+ *
+ * This routine gets the number of available display modes.
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_get_display_mode_count(void)
+#else
+int gfx_get_display_mode_count(void)
+#endif
+{
+	return(NUM_RC_DISPLAY_MODES);
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_get_frame_buffer_line_size
+ *
+ * Returns the current frame buffer line size, in bytes
+ *----------------------------------------------------------------------------  
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_frame_buffer_line_size(void)
+#else
+unsigned long gfx_get_frame_buffer_line_size(void)
+#endif
+{
+	return ((READ_REG32 (MDC_LINE_SIZE) & 0x7FF) << 3);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hactive
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_hactive(void)
+#else
+unsigned short gfx_get_hactive(void)
+#endif
+{
+	return((unsigned short)((READ_REG32(MDC_H_ACTIVE_TIMING) & 0x0FF8) + 8));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hsync_start
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_hsync_start(void)
+#else
+unsigned short gfx_get_hsync_start(void)
+#endif
+{
+	return ((unsigned short)((READ_REG32(MDC_H_SYNC_TIMING) & 0x0FF8) + 8));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hsync_end
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_hsync_end(void)
+#else
+unsigned short gfx_get_hsync_end(void)
+#endif
+{
+	return((unsigned short)(((READ_REG32(MDC_H_SYNC_TIMING) >> 16) & 0x0FF8) + 8));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_htotal
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_htotal(void)
+#else
+unsigned short gfx_get_htotal(void)
+#endif
+{
+	return((unsigned short)(((READ_REG32(MDC_H_ACTIVE_TIMING) >> 16) & 0x0FF8) + 8));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vactive
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_vactive(void)
+#else
+unsigned short gfx_get_vactive(void)
+#endif
+{
+    return((unsigned short)((READ_REG32(MDC_V_ACTIVE_TIMING) & 0x07FF) + 1));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vsync_end
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_vsync_end(void)
+#else
+unsigned short gfx_get_vsync_end(void)
+#endif
+{
+	return((unsigned short)(((READ_REG32(MDC_V_SYNC_TIMING) >> 16) & 0x07FF) + 1));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vtotal
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_vtotal(void)
+#else
+unsigned short gfx_get_vtotal(void)
+#endif
+{
+	return((unsigned short)(((READ_REG32(MDC_V_ACTIVE_TIMING) >> 16) & 0x07FF) + 1));
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_display_bpp
+ *
+ * This routine returns the current color depth of the active display.
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_display_bpp(void)
+#else
+unsigned short gfx_get_display_bpp(void)
+#endif
+{
+	unsigned long dcfg = READ_REG32 (MDC_DISPLAY_CFG);
+
+	switch ((dcfg & MDC_DCFG_DISP_MODE_MASK) >> 8)
+	{
+	    case 0: return (8);
+		case 2: return (32);
+
+		case 1: 
+			
+			switch ((dcfg & MDC_DCFG_16BPP_MODE_MASK) >> 10)
+			{
+			    case 0:  return (16);
+				case 1:  return (15);
+				case 2:  return (12);
+				default: return (0);
+			}
+	}
+
+	/* INVALID SETTING */
+
+	return (0);        
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vline
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_vline(void)
+#else
+unsigned short gfx_get_vline(void)
+#endif
+{
+	unsigned short current_scan_line;
+	
+	/* Read similar value twice to ensure that the value is not transitioning */
+	
+	do    current_scan_line  = (unsigned short)(READ_REG32(MDC_LINE_CNT_STATUS) & MDC_LNCNT_V_LINE_CNT);
+	while(current_scan_line != (unsigned short)(READ_REG32(MDC_LINE_CNT_STATUS) & MDC_LNCNT_V_LINE_CNT));
+		
+	return (current_scan_line >> 16);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_display_offset
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_display_offset(void)
+#else
+unsigned long gfx_get_display_offset(void)
+#endif
+{
+	return (READ_REG32(MDC_FB_ST_OFFSET) & 0x0FFFFFFF);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_cursor_offset
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_cursor_offset(void)
+#else
+unsigned long gfx_get_cursor_offset(void)
+#endif
+{
+	return (READ_REG32(MDC_CURS_ST_OFFSET) & 0x0FFFFFFF);
+}
+
+#if GFX_READ_ROUTINES
+
+/*************************************************************/
+/*  READ ROUTINES  |  INCLUDED FOR DIAGNOSTIC PURPOSES ONLY  */
+/*************************************************************/
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hblank_start
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_hblank_start(void)
+#else
+unsigned short gfx_get_hblank_start(void)
+#endif
+{
+	return ((unsigned short)((READ_REG32(MDC_H_BLANK_TIMING) & 0x0FF8) + 8));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hblank_end
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_hblank_end(void)
+#else
+unsigned short gfx_get_hblank_end(void)
+#endif
+{
+	return ((unsigned short)(((READ_REG32(MDC_H_BLANK_TIMING) >> 16) & 0x0FF8) + 8));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vblank_start
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_vblank_start(void)
+#else
+unsigned short gfx_get_vblank_start(void)
+#endif
+{
+	return ((unsigned short)((READ_REG32(MDC_V_BLANK_TIMING) & 0x07FF) + 1));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vsync_start
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_vsync_start(void)
+#else
+unsigned short gfx_get_vsync_start(void)
+#endif
+{
+	return ((unsigned short)((READ_REG32(MDC_V_SYNC_TIMING) & 0x07FF) + 1));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vblank_end
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_vblank_end(void)
+#else
+unsigned short gfx_get_vblank_end(void)
+#endif
+{
+	return ((unsigned short)(((READ_REG32(MDC_V_BLANK_TIMING) >> 16) & 0x07FF) + 1));
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_display_palette_entry
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_get_display_palette_entry(unsigned long index, unsigned long *palette)
+#else
+int gfx_get_display_palette_entry(unsigned long index, unsigned long *palette)
+#endif
+{
+	if (index > 0xFF)
+		return GFX_STATUS_BAD_PARAMETER;
+
+	WRITE_REG32(MDC_PAL_ADDRESS, index);
+	*palette = READ_REG32(MDC_PAL_DATA);
+	
+	return 0;
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_display_palette
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_get_display_palette(unsigned long *palette)
+#else
+void gfx_get_display_palette(unsigned long *palette)
+#endif
+{
+	unsigned long i;
+
+	WRITE_REG32(MDC_PAL_ADDRESS, 0);
+	for (i = 0; i < 256; i++)
+	{
+		palette[i] = READ_REG32(MDC_PAL_DATA);
+	}
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_cursor_enable
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_cursor_enable(void)
+#else
+unsigned long gfx_get_cursor_enable(void)
+#endif
+{
+	return (READ_REG32(MDC_GENERAL_CFG) & MDC_GCFG_CURE);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_cursor_position
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_cursor_position(void)
+#else
+unsigned long gfx_get_cursor_position(void)
+#endif
+{
+	return((READ_REG32(MDC_CURSOR_X) & 0x07FF) |
+		  ((READ_REG32(MDC_CURSOR_Y) << 16) & 0x03FF0000));
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_cursor_offset
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_cursor_clip(void)
+#else
+unsigned long gfx_get_cursor_clip(void)
+#endif
+{
+	return (((READ_REG32(MDC_CURSOR_X) >> 11) & 0x03F) |
+		    ((READ_REG32(MDC_CURSOR_Y) << 5)  & 0x3F0000));
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_cursor_color
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_cursor_color(int color)
+#else
+unsigned long gfx_get_cursor_color(int color)
+#endif
+{
+	if (color) 
+	{
+		WRITE_REG32(MDC_PAL_ADDRESS, 0x101);
+	}
+	else
+	{
+		WRITE_REG32(MDC_PAL_ADDRESS, 0x100);
+	}
+	return READ_REG32(MDC_PAL_DATA);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_icon_enable
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_icon_enable(void)
+#else
+unsigned long gfx_get_icon_enable(void)
+#endif
+{
+	return (READ_REG32(MDC_GENERAL_CFG) & MDC_GCFG_ICNE);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_icon_offset
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_icon_offset(void)
+#else
+unsigned long gfx_get_icon_offset(void)
+#endif
+{
+	return (READ_REG32(MDC_ICON_ST_OFFSET) & 0x0FFFFFFF);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_icon_position
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_icon_position(void)
+#else
+unsigned long gfx_get_icon_position(void)
+#endif
+{
+	return (READ_REG32(MDC_ICON_X) & 0x07FF);		  
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_icon_color
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_icon_color(int color)
+#else
+unsigned long gfx_get_icon_color(int color)
+#endif
+{
+	if (color >= 3)
+		return 0;
+
+	WRITE_REG32(MDC_PAL_ADDRESS, 0x102 + color);
+	
+	return READ_REG32(MDC_PAL_DATA);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_compression_enable
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_get_compression_enable(void)
+#else
+int gfx_get_compression_enable(void)
+#endif
+{
+	if (READ_REG32 (MDC_GENERAL_CFG) & MDC_GCFG_CMPE) 
+		return (1);
+	
+	return(0);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_compression_offset
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_compression_offset(void)
+#else
+unsigned long gfx_get_compression_offset(void)
+#endif
+{
+	return (READ_REG32(MDC_CB_ST_OFFSET) & 0x007FFFFF);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_compression_pitch
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_compression_pitch(void)
+#else
+unsigned short gfx_get_compression_pitch(void)
+#endif
+{
+	unsigned short pitch;
+	pitch = (unsigned short)(READ_REG32(MDC_GFX_PITCH) >> 16);
+	return (pitch << 3);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_compression_size
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned short gu2_get_compression_size(void)
+#else
+unsigned short gfx_get_compression_size(void)
+#endif
+{
+	unsigned short size;
+	size = (unsigned short)((READ_REG32(MDC_LINE_SIZE) >> 16) & 0x7F) - 1;
+	return ((size << 3) + 32);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_valid_bit
+ *-----------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_get_valid_bit(int line)
+#else
+int gfx_get_valid_bit(int line)
+#endif
+{
+	unsigned long offset;
+	int valid;
+	
+	offset  = READ_REG32 (MDC_PHY_MEM_OFFSET) & 0xFF000000;
+	offset |= line;
+
+	WRITE_REG32(MDC_PHY_MEM_OFFSET, offset);
+	valid = (int)READ_REG32 (MDC_DV_ACC) & 2;
+	
+	if (valid) return 1;
+	return 0;
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_video_offset (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_get_video_offset".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_display_video_offset(void)
+#else
+unsigned long gfx_get_display_video_offset(void)
+#endif
+{
+    return (READ_REG32(MDC_VID_Y_ST_OFFSET) & 0x0FFFFFFF);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_video_yuv_offsets (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_get_video_yuv_offsets".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_get_display_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, 
+									   unsigned long *voffset)
+#else
+void gfx_get_display_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, 
+									   unsigned long *voffset)
+#endif
+{
+    *yoffset = (READ_REG32(MDC_VID_Y_ST_OFFSET) & 0x0FFFFFFF);
+	*uoffset = (READ_REG32(MDC_VID_U_ST_OFFSET) & 0x0FFFFFFF);
+	*voffset = (READ_REG32(MDC_VID_V_ST_OFFSET) & 0x0FFFFFFF);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_video_yuv_pitch (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_get_video_yuv_pitch".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+void gu2_get_display_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch) 
+#else
+void gfx_get_display_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch)
+#endif
+{
+	unsigned long pitch = READ_REG32 (MDC_VID_YUV_PITCH);
+	
+	*ypitch = ((pitch & 0xFFFF) << 3);
+	*uvpitch = (pitch >> 13) & 0x7FFF8;
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_video_downscale_delta (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_get_video_downscale_delta".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_display_video_downscale_delta(void) 
+#else
+unsigned long gfx_get_display_video_downscale_delta(void) 
+#endif
+{
+	return (READ_REG32(MDC_VID_DS_DELTA) >> 18);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_video_downscale_enable (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_get_video_vertical_downscale_enable".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+int gu2_get_display_video_downscale_enable(void) 
+#else
+int gfx_get_display_video_downscale_enable(void) 
+#endif
+{
+	return ((int)((READ_REG32(MDC_GENERAL_CFG) >> 19) & 1));
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_video_size (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_get_video_size".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+#if GFX_DISPLAY_DYNAMIC
+unsigned long gu2_get_display_video_size(void)
+#else
+unsigned long gfx_get_display_video_size(void)
+#endif
+{
+	/* RETURN THE LINE SIZE, AS THIS IS ALL THAT IS AVAILABLE */
+
+	return((READ_REG32(MDC_LINE_SIZE) >> 21) & 0x000007FF);
+}
+
+#endif /* GFX_READ_ROUTINES */
+
+/* END OF FILE */
diff -uNr linux-2.4.31/drivers/video/nsc/gfx/durango.c linux-fb/drivers/video/nsc/gfx/durango.c
--- linux-2.4.31/drivers/video/nsc/gfx/durango.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/gfx/durango.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,497 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * This is the main file used to add Durango graphics support to a software 
+ * project.  The main reason to have a single file include the other files
+ * is that it centralizes the location of the compiler options.  This file
+ * should be tuned for a specific implementation, and then modified as needed
+ * for new Durango releases.  The releases.txt file indicates any updates to
+ * this main file, such as a new definition for a new hardware platform. 
+ *
+ * In other words, this file should be copied from the Durango source files
+ * once when a software project starts, and then maintained as necessary.  
+ * It should not be recopied with new versions of Durango unless the 
+ * developer is willing to tune the file again for the specific project.
+ *
+ * COMPILER OPTIONS
+ * These compiler options specify how the Durango routines are compiled 
+ * for the different hardware platforms.  For best performance, a driver 
+ * would build for a specific platform.  The "dynamic" switches are set 
+ * by diagnostic applications such as Darwin that will run on a variety
+ * of platforms and use the appropriate code at runtime.  Each component
+ * may be separately dynamic, so that a driver has the option of being 
+ * tuned for a specific 2D accelerator, but will still run with a variety
+ * of chipsets. 
+ * </DOC_AMD_STD>
+ */
+
+
+#define GFX_DISPLAY_DYNAMIC			1	/* runtime selection */
+#define GFX_DISPLAY_GU1				1	/* 1st generation display controller */
+#define GFX_DISPLAY_GU2				1	/* 2nd generation display controller */
+
+#define GFX_INIT_DYNAMIC            1   /* runtime selection */
+#define GFX_INIT_GU1                1   /* Geode family      */
+#define GFX_INIT_GU2                1   /* Redcloud          */
+
+#define GFX_MSR_DYNAMIC             1   /* runtime selection */
+#define GFX_MSR_REDCLOUD            1   /* Redcloud          */
+
+#define GFX_2DACCEL_DYNAMIC			1	/* runtime selection */			
+#define GFX_2DACCEL_GU1				1	/* 1st generation 2D accelerator */
+#define GFX_2DACCEL_GU2				1   /* 2nd generation 2D accelerator */
+
+#define GFX_VIDEO_DYNAMIC			1	/* runtime selection */
+#define GFX_VIDEO_CS5530			1   /* support for CS5530 */
+#define GFX_VIDEO_SC1200			1   /* support for SC1200 */
+#define GFX_VIDEO_REDCLOUD          1   /* support for Redcloud */
+
+#define GFX_VIP_DYNAMIC				1	/* runtime selection */
+#define GFX_VIP_SC1200				1   /* support for SC1200 */
+
+#define GFX_DECODER_DYNAMIC			1	/* runtime selection */
+#define GFX_DECODER_SAA7114			1	/* Philips SAA7114 decoder */
+
+#define GFX_TV_DYNAMIC				1	/* runtime selection */
+#define GFX_TV_FS451				1   /* Focus Enhancements FS450 */
+#define GFX_TV_SC1200				1   /* SC1200 integrated TV encoder */
+
+#define GFX_I2C_DYNAMIC				1	/* runtime selection */
+#define GFX_I2C_ACCESS				1   /* support for ACCESS.BUS */
+#define GFX_I2C_GPIO				1   /* support for CS5530 GPIOs */
+
+#define GFX_VGA_DYNAMIC				1	/* runtime selection */
+#define GFX_VGA_GU1					1   /* 1st generation graphics unit */
+
+#define FB4MB						1   /* Set to use 4Mb video ram for Pyramid */
+
+#define GFX_NO_IO_IN_WAIT_MACROS    0   /* Set to remove I/O accesses in GP bit testing */
+
+/* ROUTINES TO READ VALUES
+ * These are routines used by Darwin or other diagnostics to read the 
+ * current state of the hardware.  Display drivers or embedded applications can 
+ * reduce the size of the Durango code by not including these routines. 
+ */
+#define GFX_READ_ROUTINES			1	/* add routines to read values */
+
+/* VARIABLES USED FOR RUNTIME SELECTION
+ * If part of the graphics subsystem is declared as dynamic, then the 
+ * following variables are used to specify which platform has been detected.
+ * The variables are set in the "gfx_detect_cpu" routine.  The values should 
+ * be bit flags to allow masks to be used to check for multiple platforms.
+ */
+
+#if GFX_DISPLAY_DYNAMIC
+int gfx_display_type = 0;
+#endif
+
+#if GFX_INIT_DYNAMIC
+int gfx_init_type = 0;
+#endif
+
+#if GFX_MSR_DYNAMIC
+int gfx_msr_type = 0;
+#endif
+
+#if GFX_2DACCEL_DYNAMIC
+int gfx_2daccel_type = 0;
+#endif
+
+#if GFX_VIDEO_DYNAMIC
+int gfx_video_type = 0;
+#endif
+
+#if GFX_VIP_DYNAMIC
+int gfx_vip_type = 0;
+#endif
+
+#if GFX_DECODER_DYNAMIC
+int gfx_decoder_type = 0;
+#endif
+
+#if GFX_TV_DYNAMIC
+int gfx_tv_type = 0;
+#endif
+
+#if GFX_I2C_DYNAMIC
+int gfx_i2c_type = 0;
+#endif
+
+#if GFX_VGA_DYNAMIC
+int gfx_vga_type = 0;
+#endif
+
+/* HEADER FILE FOR DURANGO ROUTINE DEFINITIONS
+ * Needed since some of the Durango routines call other Durango routines.
+ * Also defines the size of chipset array (GFX_CSPTR_SIZE).
+ */
+#include "gfx_rtns.h"		/* routine definitions */
+
+/* INCLUDE PROTOTYPES FOR PRIVATE ROUTINES */
+
+#include "gfx_priv.h"
+
+/* DEFINE POINTERS TO MEMORY MAPPED REGIONS
+ * These pointers are used by the Durango routines to access the hardware. 
+ * The variables must be set by the project's initialization code after
+ * mapping the regions in the appropriate manner. 
+ */
+
+/* DEFINE VIRTUAL ADDRESSES */
+/* Note: These addresses define the starting base expected by all    */
+/*       Durango offsets.  Under an OS that requires these pointers  */
+/*       to be mapped to linear addresses (i.e Windows), it may not  */
+/*       be possible to keep these base offsets.  In these cases,    */
+/*       the addresses are modified to point to the beginning of the */
+/*       relevant memory region and the access macros are adjusted   */
+/*       to subtract the offset from the default base.  For example, */
+/*       the register pointer could be moved to be 0x40008000, while */
+/*       the WRITE_REG* macros are modified to subtract 0x8000 from  */
+/*       the offset.                                                 */
+
+unsigned char *gfx_virt_regptr = (unsigned char *) 0x40000000;
+unsigned char *gfx_virt_fbptr  = (unsigned char *) 0x40800000;
+unsigned char *gfx_virt_vidptr = (unsigned char *) 0x40010000;
+unsigned char *gfx_virt_vipptr = (unsigned char *) 0x40015000;
+unsigned char *gfx_virt_spptr  = (unsigned char *) 0x40000000;
+unsigned char *gfx_virt_gpptr  = (unsigned char *) 0x40000000;
+
+/* DEFINE PHYSICAL ADDRESSES */
+
+unsigned char *gfx_phys_regptr = (unsigned char *) 0x40000000;
+unsigned char *gfx_phys_fbptr  = (unsigned char *) 0x40800000;
+unsigned char *gfx_phys_vidptr = (unsigned char *) 0x40010000;
+unsigned char *gfx_phys_vipptr = (unsigned char *) 0x40015000;
+
+/* HEADER FILE FOR GRAPHICS REGISTER DEFINITIONS 
+ * This contains only constant definitions, so it should be able to be 
+ * included in any software project as is.
+ */
+#include "gfx_regs.h"		/* graphics register definitions */
+
+/* HEADER FILE FOR REGISTER ACCESS MACROS
+ * This file contains the definitions of the WRITE_REG32 and similar macros
+ * used by the Durango routines to access the hardware.  The file assumes 
+ * that the environment can handle 32-bit pointer access.  If this is not
+ * the case, or if there are special requirements, then this header file 
+ * should not be included and the project must define the macros itself.
+ * (A project may define WRITE_REG32 to call a routine, for example).
+ */	
+#include "gfx_defs.h"		/* register access macros */
+
+/* IO MACROS AND ROUTINES
+ * These macros must be defined before the initialization or I2C 
+ * routines will work properly. 
+ */
+
+#if defined(OS_WIN32)	/* For Windows */
+
+/* VSA II CALL */
+
+void gfx_msr_asm_read (unsigned short msrReg, unsigned long msrAddr, unsigned long *ptrHigh, unsigned long *ptrLow)
+{
+	unsigned long temp1, temp2;
+
+	_asm {
+		mov     dx, 0x0AC1C
+		mov     eax, 0x0FC530007
+		out     dx, eax
+
+		add     dl, 2
+		mov     ecx, msrAddr
+		mov		cx, msrReg
+		in      ax, dx
+
+		; EDX:EAX will contain MSR contents.
+
+		mov		temp1, edx
+		mov     temp2, eax
+	}
+
+	*ptrHigh = temp1;
+	*ptrLow  = temp2;
+}
+
+void gfx_msr_asm_write (unsigned short msrReg, unsigned long msrAddr, unsigned long *ptrHigh, unsigned long *ptrLow)
+{
+	unsigned long temp1 = *ptrHigh;
+	unsigned long temp2 = *ptrLow;
+
+	_asm {
+
+		mov     dx, 0x0AC1C
+		mov     eax, 0x0FC530007
+		out     dx, eax
+    
+		add     dl, 2
+		mov     ecx, msrAddr			; ECX contains msrAddr | msrReg
+		mov		cx, msrReg				;
+	    mov     ebx, temp1				; <OR_mask_hi>
+	    mov     eax, temp2				; <OR_mask_hi>
+
+	    mov     esi, 0					; <AND_mask_hi>
+	    mov     edi, 0					; <AND_mask_lo>
+	    out     dx, ax	
+
+		; MSR is written at this point
+	}
+}
+
+unsigned char gfx_inb(unsigned short port)
+{
+	unsigned char data;
+	_asm {
+		pushf
+		mov		dx, port
+		in		al, dx
+		mov		data, al
+		popf
+	}
+	return(data);
+}
+
+unsigned short gfx_inw(unsigned short port)
+{
+	unsigned short data;
+	_asm {
+		pushf
+		mov		dx, port
+		in		ax, dx
+		mov		data, ax
+		popf
+	}
+	return(data);
+}
+
+unsigned long gfx_ind(unsigned short port)
+{
+	unsigned long data;
+	_asm {
+		pushf
+		mov		dx, port
+		in		eax, dx
+		mov		data, eax
+		popf
+	}
+	return(data);
+}
+
+void gfx_outb(unsigned short port, unsigned char data)
+{
+	_asm {
+		pushf
+		mov		al, data
+		mov		dx, port
+		out		dx, al
+		popf
+	}
+}
+
+void gfx_outw(unsigned short port, unsigned short data)
+{
+	_asm {
+		pushf
+		mov		ax, data
+		mov		dx, port
+		out		dx, ax
+		popf
+	}
+}
+
+void gfx_outd(unsigned short port, unsigned long data)
+{
+	_asm {
+		pushf
+		mov		eax, data
+		mov		dx, port
+		out		dx, eax
+		popf
+	}
+}
+
+#elif defined(OS_VXWORKS) || defined (OS_LINUX) /* VxWorks and Linux */
+
+#if defined(OS_LINUX)
+#include "asm/msr.h"
+#endif
+
+void gfx_msr_asm_read (unsigned short msrReg, unsigned long msrAddr, unsigned long *ptrHigh, unsigned long *ptrLow)
+{
+	unsigned long addr, val1, val2;
+
+	addr = msrAddr | (unsigned long)msrReg;
+	rdmsr(addr, val1, val2);
+
+	*ptrHigh = val2;
+	*ptrLow  = val1;
+}
+
+void gfx_msr_asm_write (unsigned short msrReg, unsigned long msrAddr, unsigned long *ptrHigh, unsigned long *ptrLow)
+{
+	unsigned long addr, val1, val2;
+
+	val2 = *ptrHigh;
+	val1 = *ptrLow;
+
+	addr = (msrAddr & 0xFFFF0000) | (unsigned long)msrReg;
+	wrmsr(addr, val1, val2);
+}
+
+unsigned char gfx_inb(unsigned short port)
+{
+	unsigned char value;
+    __asm__ volatile ("inb %1,%0" : "=a" (value) : "d" (port));
+    return value;
+}
+
+unsigned short gfx_inw(unsigned short port)
+{
+	unsigned short value;
+    __asm__ volatile ("in %1,%0" : "=a" (value) : "d" (port));
+    return value;
+}
+
+unsigned long gfx_ind(unsigned short port)
+{
+	unsigned long value;
+    __asm__ volatile ("inl %1,%0" : "=a" (value) : "d" (port));
+    return value;
+}
+
+void gfx_outb(unsigned short port, unsigned char data)
+{
+	__asm__ volatile ("outb %0,%1" : : "a" (data),"d" (port));
+}
+
+void gfx_outw(unsigned short port, unsigned short data)
+{
+	__asm__ volatile ("out %0,%1" : : "a" (data),"d" (port));
+}
+
+void gfx_outd(unsigned short port, unsigned long data)
+{
+	__asm__ volatile ("outl %0,%1" : : "a" (data),"d" (port));
+}
+
+#else /* else nothing */
+
+unsigned char gfx_inb(unsigned short port)
+{
+	/* ADD OS SPECIFIC IMPLEMENTATION */
+	return(0);
+}
+
+unsigned short gfx_inw(unsigned short port)
+{
+	/* ADD OS SPECIFIC IMPLEMENTATION */
+	return(0);
+}
+
+unsigned long gfx_ind(unsigned short port)
+{
+	/* ADD OS SPECIFIC IMPLEMENTATION */
+	return(0);
+}
+
+void gfx_outb(unsigned short port, unsigned char data)
+{
+	/* ADD OS SPECIFIC IMPLEMENTATION */
+}
+
+void gfx_outw(unsigned short port, unsigned short data)
+{
+	/* ADD OS SPECIFIC IMPLEMENTATION */
+}
+
+void gfx_outd(unsigned short port, unsigned long data)
+{
+	/* ADD OS SPECIFIC IMPLEMENTATION */
+}
+#endif
+
+#define INB(port) gfx_inb(port)
+#define INW(port) gfx_inw(port)
+#define IND(port) gfx_ind(port)
+#define OUTB(port, data) gfx_outb(port, data)
+#define OUTW(port, data) gfx_outw(port, data)
+#define OUTD(port, data) gfx_outd(port, data)
+
+/* INITIALIZATION ROUTINES 
+ * These routines are used during the initialization of the driver to 
+ * perform such tasks as detecting the type of CPU and video hardware.  
+ * The routines require the use of IO, so the above IO routines need 
+ * to be implemented before the initialization routines will work
+ * properly.
+ */
+
+#include "gfx_init.c"    
+
+/* INCLUDE MSR ACCESS ROUTINES */
+
+#include "gfx_msr.c"
+
+/* INCLUDE GRAPHICS ENGINE ROUTINES 
+ * These routines are used to program the 2D graphics accelerator.  If
+ * the project does not use graphics acceleration (direct frame buffer
+ * access only), then this file does not need to be included. 
+ */
+#include "gfx_rndr.c"		/* graphics engine routines */
+
+/* INCLUDE DISPLAY CONTROLLER ROUTINES 
+ * These routines are used if the display mode is set directly.  If the 
+ * project uses VGA registers to set a display mode, then these files
+ * do not need to be included.
+ */
+#include "gfx_mode.h"		/* display mode tables */
+#include "gfx_disp.c"		/* display controller routines */
+
+/* INCLUDE VIDEO OVERLAY ROUTINES
+ * These routines control the video overlay hardware. 
+ */
+#include "gfx_vid.c"		/* video overlay routines */
+
+/* VIDEO PORT AND VIDEO DECODER ROUTINES
+ * These routines rely on the I2C routines.
+ */
+#include "gfx_vip.c"		/* video port routines */
+#include "gfx_dcdr.c"		/* video decoder routines */
+
+/* I2C BUS ACCESS ROUTINES
+ * These routines are used by the video decoder and possibly an 
+ * external TV encoer. 
+ */
+#include "gfx_i2c.c"		/* I2C bus access routines */
+
+/* TV ENCODER ROUTINES
+ * This file does not need to be included if the system does not
+ * support TV output.
+ */
+#include "gfx_tv.c"		    /* TV encoder routines */
+
+/* VGA ROUTINES
+ * This file is used if setting display modes using VGA registers.
+ */
+#include "gfx_vga.c"		/* VGA routines */
+
+/* END OF FILE */
diff -uNr linux-2.4.31/drivers/video/nsc/gfx/gfx_dcdr.c linux-fb/drivers/video/nsc/gfx/gfx_dcdr.c
--- linux-2.4.31/drivers/video/nsc/gfx/gfx_dcdr.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/gfx/gfx_dcdr.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,448 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * This file contains routines to control the video decoder.
+ * 
+ *    gfx_set_decoder_defaults
+ *    gfx_set_decoder_analog_input
+ *    gfx_set_decoder_brightness
+ *    gfx_set_decoder_contrast	
+ *    gfx_set_decoder_luminance_filter
+ *    gfx_set_decoder_hue
+ *    gfx_set_decoder_saturation
+ *    gfx_set_decoder_input_offset
+ *    gfx_set_decoder_input_size
+ *    gfx_set_decoder_output_size
+ *    gfx_set_decoder_scale
+ *    gfx_set_decoder_TV_standard
+ *    gfx_set_decoder_vbi_enable
+ *    gfx_set_decoder_vbi_format
+ *    gfx_set_decoder_vbi_upscale
+ *    gfx_decoder_software_reset
+ *    gfx_decoder_detect_macrovision
+ *    gfx_decoder_detect_video
+ *
+ * And the following routines if GFX_READ_ROUTINES is set:
+ *
+ *    gfx_get_decoder_brightness
+ *    gfx_get_decoder_contrast
+ *    gfx_get_decoder_hue
+ *    gfx_get_decoder_saturation
+ *    gfx_get_decoder_input_offset
+ *    gfx_get_decoder_input_size
+ *    gfx_get_decoder_output_size
+ *    gfx_get_decoder_vbi_format
+ * </DOC_AMD_STD>
+ */
+
+
+
+/* INCLUDE SUPPORT FOR PHILIPS SAA7114 DECODER, IF SPECIFIED */
+
+#if GFX_DECODER_SAA7114
+#include "saa7114.c"
+#endif
+
+/* WRAPPERS IF DYNAMIC SELECTION */
+/* Extra layer to call various decoders.  Currently only the Pillips */
+/* decoder is supported, but still organized to easily expand later. */
+
+#if GFX_DECODER_DYNAMIC
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_defaults
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_defaults(void)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_defaults();
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_analog_input
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_analog_input(unsigned char input)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_analog_input(input);
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_brightness
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_brightness(unsigned char brightness)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_brightness(brightness);
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_contrast
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_contrast(unsigned char contrast)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_contrast(contrast);
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_hue
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_hue(char hue)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_hue(hue);
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_saturation
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_saturation(unsigned char saturation)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_saturation(saturation);
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_input_offset
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_input_offset(unsigned short x, unsigned short y)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_input_offset(x, y);
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_input_size
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_input_size(unsigned short width, unsigned short height)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_input_size(width, height);
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_output_size
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_output_size(unsigned short width, unsigned short height)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_output_size(width, height);
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_scale
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_scale(unsigned short srcw, unsigned short srch, 
+	unsigned short dstw, unsigned short dsth)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_scale(srcw, srch, dstw, dsth);
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_vbi_format
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_vbi_format(int start, int end, int format)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_vbi_format(start, end, format);
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_vbi_enable
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_vbi_enable(int enable)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_vbi_enable(enable);
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_vbi_upscale
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_vbi_upscale(void)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_vbi_upscale();
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_TV_standard
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_TV_standard(TVStandardType TVStandard)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_TV_standard(TVStandard);
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_set_decoder_luminance_filter
+ *-----------------------------------------------------------------------------
+ */
+int gfx_set_decoder_luminance_filter(unsigned char lufi)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_set_decoder_luminance_filter(lufi);
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_decoder_software_reset
+ *-----------------------------------------------------------------------------
+ */
+int gfx_decoder_software_reset(void)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_decoder_software_reset();
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_decoder_detect_macrovision
+ *-----------------------------------------------------------------------------
+ */
+int gfx_decoder_detect_macrovision(void)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_decoder_detect_macrovision();
+#endif
+	return(status);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_decoder_detect_video
+ *-----------------------------------------------------------------------------
+ */
+int gfx_decoder_detect_video(void)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		status = saa7114_decoder_detect_video();
+#endif
+	return(status);
+}
+
+/*************************************************************/
+/*  READ ROUTINES  |  INCLUDED FOR DIAGNOSTIC PURPOSES ONLY  */
+/*************************************************************/
+
+#if GFX_READ_ROUTINES
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_decoder_brightness
+ *-----------------------------------------------------------------------------
+ */
+unsigned char gfx_get_decoder_brightness(void)
+{
+	unsigned char brightness = 0;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		brightness = saa7114_get_decoder_brightness();
+#endif
+	return(brightness);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_decoder_contrast
+ *-----------------------------------------------------------------------------
+ */
+unsigned char gfx_get_decoder_contrast(void)
+{
+	unsigned char contrast = 0;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		contrast = saa7114_get_decoder_contrast();
+#endif
+	return(contrast);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_decoder_hue
+ *-----------------------------------------------------------------------------
+ */
+char gfx_get_decoder_hue(void)
+{
+	unsigned char hue = 0;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		hue = saa7114_get_decoder_hue();
+#endif
+	return((char)hue);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_decoder_saturation
+ *-----------------------------------------------------------------------------
+ */
+unsigned char gfx_get_decoder_saturation(void)
+{
+	unsigned char saturation = 0;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		saturation = saa7114_get_decoder_saturation();
+#endif
+	return(saturation);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_decoder_input_offset
+ *-----------------------------------------------------------------------------
+ */
+unsigned long gfx_get_decoder_input_offset()
+{
+	unsigned long offset = 0;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		offset = saa7114_get_decoder_input_offset();
+#endif
+	return(offset);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_decoder_input_size
+ *-----------------------------------------------------------------------------
+ */
+unsigned long gfx_get_decoder_input_size()
+{
+	unsigned long size = 0;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		size = saa7114_get_decoder_input_size();
+#endif
+	return(size);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_decoder_output_size
+ *-----------------------------------------------------------------------------
+ */
+unsigned long gfx_get_decoder_output_size()
+{
+	unsigned long size = 0;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		size = saa7114_get_decoder_output_size();
+#endif
+	return(size);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_decoder_vbi_format
+ *-----------------------------------------------------------------------------
+ */
+int gfx_get_decoder_vbi_format(int line)
+{
+	int format = 0;
+#if GFX_DECODER_SAA7114
+	if (gfx_decoder_type == GFX_DECODER_SAA7114)
+		format = saa7114_get_decoder_vbi_format(line);
+#endif
+	return(format);
+}
+
+#endif /* GFX_READ_ROUTINES */
+
+#endif /* GFX_DECODER_DYNAMIC */
+
+/* END OF FILE */
diff -uNr linux-2.4.31/drivers/video/nsc/gfx/gfx_defs.h linux-fb/drivers/video/nsc/gfx/gfx_defs.h
--- linux-2.4.31/drivers/video/nsc/gfx/gfx_defs.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/gfx/gfx_defs.h	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,331 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ *
+ * This header file contains the macros used to access the hardware.  These
+ * macros assume that 32-bit access is possible, which is true for most 
+ * applications.  Projects using 16-bit compilers (the Windows98 display
+ * driver) and special purpose applications (such as Darwin) need to define 
+ * their own versions of these macros, which typically call a subroutine.
+ *
+ * </DOC_AMD_STD>
+ */
+
+/* ACCESS TO THE CPU REGISTERS */
+ 
+#define WRITE_REG8(offset, value) \
+	(*(volatile unsigned char *)(gfx_virt_regptr + (offset))) = (value)
+
+#define WRITE_REG16(offset, value) \
+	(*(volatile unsigned short *)(gfx_virt_regptr + (offset))) = (value)
+
+#define WRITE_REG32(offset, value) \
+	(*(volatile unsigned long *)(gfx_virt_regptr + (offset))) = (value)
+
+#define READ_REG16(offset) \
+    (*(volatile unsigned short *)(gfx_virt_regptr + (offset)))
+
+#define READ_REG32(offset) \
+    (*(volatile unsigned long *)(gfx_virt_regptr + (offset)))
+
+/* ACCESS TO THE ACCELERATOR REGISTERS (REDCLOUD ONLY) */
+
+#define WRITE_GP8(offset, value) \
+	(*(volatile unsigned char *)(gfx_virt_gpptr + (offset))) = (value)
+
+#define WRITE_GP16(offset, value) \
+	(*(volatile unsigned short *)(gfx_virt_gpptr + (offset))) = (value)
+
+#define WRITE_GP32(offset, value) \
+	(*(volatile unsigned long *)(gfx_virt_gpptr + (offset))) = (value)
+
+#define READ_GP16(offset) \
+    (*(volatile unsigned short *)(gfx_virt_gpptr + (offset)))
+
+#define READ_GP32(offset) \
+    (*(volatile unsigned long *)(gfx_virt_gpptr + (offset)))
+
+/* ACCESS TO THE FRAME BUFFER */
+
+#define WRITE_FB32(offset, value) \
+	(*(volatile unsigned long *)(gfx_virt_fbptr + (offset))) = (value)
+
+#define WRITE_FB16(offset, value) \
+	(*(volatile unsigned short *)(gfx_virt_fbptr + (offset))) = (value)
+
+#define WRITE_FB8(offset, value) \
+	(*(volatile unsigned char *)(gfx_virt_fbptr + (offset))) = (value)
+
+/* ACCESS TO THE VIDEO HARDWARE */
+
+#define READ_VID32(offset) \
+	(*(volatile unsigned long *)(gfx_virt_vidptr + (offset)))
+
+#define WRITE_VID32(offset, value) \
+	(*(volatile unsigned long *)(gfx_virt_vidptr + (offset))) = (value)
+
+/* ACCESS TO THE VIP HARDWARE */
+
+#define READ_VIP32(offset) \
+	(*(volatile unsigned long *)(gfx_virt_vipptr + (offset)))
+
+#define WRITE_VIP32(offset, value) \
+	(*(volatile unsigned long *)(gfx_virt_vipptr + (offset))) = (value)
+
+/* ACCESS TO THE SCRATCHPAD RAM */
+
+#define WRITE_SCRATCH32(offset, value) \
+	(*(volatile unsigned long *)(gfx_virt_spptr + (offset))) = (value)
+
+#define WRITE_SCRATCH16(offset, value) \
+	(*(volatile unsigned short *)(gfx_virt_spptr + (offset))) = (value)
+
+#define WRITE_SCRATCH8(offset, value) \
+	(*(volatile unsigned char *)(gfx_virt_spptr + (offset))) = (value)
+
+#define READ_SCRATCH16(offset) \
+    (*(volatile unsigned short *)(gfx_virt_spptr + (offset)))
+
+#define READ_SCRATCH32(offset) \
+    (*(volatile unsigned long *)(gfx_virt_spptr + (offset)))
+
+/* ACCESS TO MSRS */
+
+void gfx_msr_asm_write (unsigned short msrReg, unsigned long msrAddr, unsigned long *ptrHigh, unsigned long *ptrLow);
+void gfx_msr_asm_read (unsigned short msrReg, unsigned long msrAddr, unsigned long *ptrHigh, unsigned long *ptrLow);
+
+#define MSR_READ( MBD_MSR_CAP, address, valueHigh_ptr, valueLow_ptr ) \
+					 gfx_msr_asm_read( ((unsigned short)(MBD_MSR_CAP)), address, valueHigh_ptr, valueLow_ptr )
+
+#define MSR_WRITE( MBD_MSR_CAP, address, valueHigh_ptr, valueLow_ptr ) \
+					 gfx_msr_asm_write( ((unsigned short)(MBD_MSR_CAP)), address, valueHigh_ptr, valueLow_ptr )
+
+/* OPTIMIZATION MACROS */
+/* The following macros have been added to allow more complete optimization of the */
+/* bitmap-to-screen routines in Durango.  These routines also allow Durango to run */
+/* properly within a 16-bit environment.                                           */
+
+/************************************************************************************
+ * Macro:   SET_SCRATCH_BASE 
+ * Purpose: Record the base address of the BLT buffers.  The WRITE_SCRATCH_STRINGxx 
+ *          macros assume that this address is used as the base for all writes.
+ *                                                         
+ * Arguments:                                              
+ *    scratch_base -   offset into the GX base for the first BLT buffer byte.
+ ************************************************************************************/
+
+#define SET_SCRATCH_BASE(scratch_base) \
+	{ gfx_gx1_scratch_base = (unsigned long)gfx_virt_spptr + scratch_base; }
+
+#ifdef GFX_OPTIMIZE_ASSEMBLY
+
+/************************************************************************************
+ * Macro:   WRITE_SCRATCH_STRING  
+ * Purpose: Write multiple bytes to the scratchpad buffer 
+ *                                                         
+ * Arguments:                                              
+ *    dword_bytes  -   number of bytes to transfer.  This number will always.
+ *                     be a multiple of 4.  It cannot be modified within the 
+ *                     macro (ex. bytes -= 4)
+ *    bytes_extra  -   number of non-DWORD aligned bytes
+ *    array        -   pointer to an array of unsigned characters. 
+ *    array_offset -   offset into the array from which to pull the first character.
+ ************************************************************************************/
+
+#define WRITE_SCRATCH_STRING(dwords, bytes, array, array_offset)                            \
+{                                                                                           \
+	_asm { mov edi, gfx_gx1_scratch_base }                                                  \
+	_asm { mov esi, array }                                                                 \
+	_asm { add esi, array_offset }                                                          \
+	_asm { mov ecx, dwords }                                                                \
+	_asm { shr ecx, 2 }                                                                     \
+	_asm { rep movsd }                                                                      \
+	_asm { mov ecx, bytes }                                                                 \
+	_asm { rep movsb }                                                                      \
+}
+
+/************************************************************************************
+ * Macro:   WRITE_FRAME_BUFFER_STRING32  
+ * Purpose: Write multiple dwords to the Frame buffer 
+ *                                                         
+ * Arguments:                                              
+ *    fboffset     -   offset to the beginning frame buffer location.
+ *    bytes        -   number of bytes to transfer.  This number will always.
+ *                     be a multiple of 4.  It cannot be modified within the 
+ *                     macro (ex. bytes -= 4)
+ *    array        -   pointer to an array of unsigned characters. 
+ *    array_offset -   offset into the array from which to pull the first character.
+ ************************************************************************************/
+
+#define WRITE_FRAME_BUFFER_STRING32(fboffset, bytes, array, array_offset)                \
+{                                                                                        \
+	_asm { mov ecx, bytes }                                                              \
+	_asm { shr ecx, 2 }                                                                  \
+	_asm { cld }                                                                         \
+	_asm { mov edi, gfx_virt_fbptr }                                                     \
+	_asm { add edi, fboffset }                                                           \
+	_asm { mov esi, array }                                                              \
+	_asm { add esi, array_offset }                                                       \
+    _asm { rep movsd }                                                                   \
+}
+
+#else
+
+/************************************************************************************
+ * Macro:   WRITE_SCRATCH_STRING  
+ * Purpose: Write multiple bytes to the scratchpad buffer 
+ *                                                         
+ * Arguments:                                              
+ *    dword_bytes  -   number of bytes to transfer.  This number will always.
+ *                     be a multiple of 4.  It cannot be modified within the 
+ *                     macro (ex. bytes -= 4)
+ *    bytes_extra  -   number of non-DWORD aligned bytes
+ *    array        -   pointer to an array of unsigned characters. 
+ *    array_offset -   offset into the array from which to pull the first character.
+ ************************************************************************************/
+
+#define WRITE_SCRATCH_STRING(dword_bytes, bytes_extra, array, array_offset)                             \
+{                                                                                                       \
+	unsigned long i, j;                                                                                 \
+	unsigned long aroffset = (unsigned long)array + (array_offset);                                     \
+	                                                                                                    \
+	/* WRITE DWORDS */                                                                                  \
+	                                                                                                    \
+	for (i = 0; i < dword_bytes; i += 4)                                                                \
+		*((volatile unsigned long *)(gfx_gx1_scratch_base + i)) = *((unsigned long *)(aroffset + i));   \
+	                                                                                                    \
+	/* WRITE BYTES */                                                                                   \
+	                                                                                                    \
+	j = i + bytes_extra;	                                                                            \
+	while (i < j)	                                                                                    \
+	{	                                                                                    \
+		*((volatile unsigned char *)(gfx_gx1_scratch_base + i)) = *((unsigned char *)(aroffset + i));   \
+		i++;	                                                                                    \
+	}	                                                                                    \
+}
+
+/************************************************************************************
+ * Macro:   WRITE_FRAME_BUFFER_STRING32  
+ * Purpose: Write multiple dwords to the Frame buffer 
+ *                                                         
+ * Arguments:                                              
+ *    fboffset     -   offset to the beginning frame buffer location.
+ *    bytes        -   number of bytes to transfer.  This number will always.
+ *                     be a multiple of 4.  It cannot be modified within the 
+ *                     macro (ex. bytes -= 4)
+ *    array        -   pointer to an array of unsigned characters. 
+ *    array_offset -   offset into the array from which to pull the first character.
+ ************************************************************************************/
+
+#define WRITE_FRAME_BUFFER_STRING32(fboffset, bytes, array, array_offset)                         \
+{                                                                                            \
+	unsigned long i;                                                                         \
+	unsigned long aroffset = (unsigned long)array + (array_offset);                          \
+	for (i = 0; i < bytes; i += 4)                                                           \
+		WRITE_FB32 ((fboffset) + i, *((unsigned long *)(aroffset + i)));                \
+}
+
+#endif
+
+/************************************************************************************
+ * Macro:   WRITE_FRAME_BUFFER_STRING8  
+ * Purpose: Write multiple bytes to the frame buffer 
+ *                                                         
+ * Arguments:                                              
+ *    spoffset     -   offset to the beginning frame buffer location.
+ *    bytes        -   number of bytes to transfer.  This number cannot be modified within the 
+ *                     macro (ex. bytes -= 4)
+ *    array        -   pointer to an array of unsigned characters. 
+ *    array_offset -   offset into the array from which to pull the first character.
+ ************************************************************************************/
+
+#define WRITE_FRAME_BUFFER_STRING8(fboffset, bytes, array, array_offset)                          \
+{                                                                                            \
+	unsigned long i;                                                                         \
+	unsigned long aroffset = (unsigned long)array + (array_offset);                          \
+	for (i = 0; i < bytes; i++)                                                              \
+		WRITE_FB8 ((fboffset) + i, *((unsigned char *)(aroffset + i)));                      \
+}
+
+/************************************************************************************
+ * Macro:   WRITE_GPREG_STRING32
+ * Purpose: Write multiple dwords to one GP register.
+ *                                                         
+ * Arguments:                                              
+ *    regoffset    -   Offset of the GP register to be written.
+ *    dwords       -   number of dwords to transfer.  It cannot be modified within the 
+ *                     macro (ex. dwords--)
+ *    counter      -   name of a counter variable that can be used in a loop.  This
+ *                     is used to optimize macros written in C.
+ *    array        -   pointer to an array of unsigned characters. 
+ *    array_offset -   offset into the array from which to pull the first character.
+ *    temp         -   name of a temporary variable that can be used for calculations.
+ *                     This argument is also used for C-only macros.
+ ************************************************************************************/
+
+#define WRITE_GPREG_STRING32(regoffset, dwords, counter, array, array_offset, temp)           \
+{                                                                                            \
+	temp = (unsigned long)array + (array_offset);                                            \
+	for (counter = 0; counter < dwords; counter++)                                         \
+		WRITE_GP32 (regoffset, *((unsigned long *)temp + counter));                        \
+}
+
+/************************************************************************************
+ * Macro:   WRITE_GPREG_STRING8
+ * Purpose: Write 4 or less bytes to one GP register.
+ *                                                         
+ * Arguments:                                              
+ *    regoffset    -   Offset of the GP register to be written.
+ *    bytes        -   number of bytes to transfer.  This number will always.
+ *                     be less than 4.  It cannot be modified within the 
+ *                     macro (ex. bytes--)
+ *    shift        -   name of a shift variable that can be used as a shift count.
+ *                     This variable holds the initial shift value into the GP register.
+ *    counter      -   name of a counter variable that can be used in a loop.  This
+ *                     is used to optimize macros written in C.
+ *    array        -   pointer to an array of unsigned characters. 
+ *    array_offset -   offset into the array from which to pull the first character.
+ *    temp1        -   name of a temporary variable that can be used for calculations.
+ *                     This argument is also used for C-only macros.
+ *    temp2        -   name of a temporary variable that can be used for calculations.
+ *                     This argument is also used for C-only macros.
+ ************************************************************************************/
+#define WRITE_GPREG_STRING8(regoffset, bytes, shift, counter, array, array_offset, temp1, temp2)           \
+{                                                                                           \
+	if (bytes)                                                                              \
+	{                                                                                       \
+		temp1 = (unsigned long)array + (array_offset);                                      \
+		temp2 = 0;                                                                          \
+		for (counter = 0; counter < bytes; counter++)                                       \
+		{                                                                                   \
+			temp2 |= ((unsigned long)(*((unsigned char *)(temp1 + counter)))) << shift;     \
+			shift += 8;                                                                     \
+		}                                                                                   \
+		WRITE_GP32 (regoffset, temp2);                                                      \
+	}                                                                                       \
+}
+
+
+/* END OF FILE */
+
diff -uNr linux-2.4.31/drivers/video/nsc/gfx/gfx_disp.c linux-fb/drivers/video/nsc/gfx/gfx_disp.c
--- linux-2.4.31/drivers/video/nsc/gfx/gfx_disp.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/gfx/gfx_disp.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,2052 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * This file contains routines to program the display controller.  
+ *
+ * The "disp_gu1.c" and "disp_gu2.c" files implement the following routines:
+ *
+ *    gfx_get_display_mode_count
+ *    gfx_get_display_mode
+ *    gfx_is_display_mode_supported
+ *    gfx_get_display_details
+ *    gfx_set_display_mode
+ *    gfx_set_display_bpp
+ *	  gfx_set_display_timings
+ *    gfx_set_vtotal
+ *    gfx_get_display_pitch
+ *    gfx_set_display_pitch
+ *    gfx_set_display_offset
+ *    gfx_set_display_palette
+ *    gfx_set_display_palette_entry
+ *    gfx_set_cursor_enable
+ *    gfx_set_cursor_colors
+ *    gfx_set_cursor_position
+ *	  gfx_set_cursor_shape32
+ *	  gfx_set_cursor_shape64
+ *    gfx_set_icon_enable
+ *    gfx_set_icon_colors
+ *    gfx_set_icon_position
+ *    gfx_set_icon_shape64
+ *    gfx_set_compression_enable
+ *    gfx_set_compression_offset
+ *    gfx_set_compression_pitch
+ *    gfx_set_compression_size
+ *    gfx_set_display_priority_high
+ *    gfx_test_timing_active
+ *    gfx_test_vertical_active
+ *    gfx_wait_vertical_blank
+ *    gfx_reset_timing_lock
+ *
+ * And the following routines if GFX_READ_ROUTINES is set:
+ *	
+ *	  gfx_get_hactive
+ *    gfx_get_hblank_start
+ *    gfx_get_hsync_start
+ *    gfx_get_hsync_end
+ *    gfx_get_hblank_end
+ *    gfx_get_htotal
+ *    gfx_get_vactive
+ *    gfx_get_vblank_start
+ *    gfx_get_vsync_start
+ *    gfx_get_vsync_end
+ *    gfx_get_vblank_end
+ *    gfx_get_vtotal
+ *    gfx_get_vline
+ *    gfx_get_display_bpp
+ *    gfx_get_display_offset
+ *    gfx_get_display_palette
+ *    gfx_get_cursor_enable
+ *    gfx_get_cursor_base
+ *    gfx_get_cursor_position
+ *    gfx_get_cursor_offset
+ *    gfx_get_cursor_color
+ *    gfx_get_icon_enable
+ *    gfx_get_icon_color
+ *    gfx_get_icon_offset
+ *    gfx_get_icon_position
+ *    gfx_get_compression_enable
+ *    gfx_get_compression_offset
+ *    gfx_get_compression_pitch
+ *    gfx_get_compression_size
+ *    gfx_get_display_priority_high
+ *    gfx_get_valid_bit
+ * </DOC_AMD_STD>
+ */
+
+
+unsigned short PanelWidth=0;
+unsigned short PanelHeight=0;
+unsigned short PanelEnable=0;
+unsigned short ModeWidth; 
+unsigned short ModeHeight;
+
+int	DeltaX=0;
+int	DeltaY=0;
+unsigned long prevstartAddr =0;
+unsigned long panelTop      =0;
+unsigned long panelLeft     =0;
+
+int gbpp=8;
+
+int gfx_compression_enabled = 0;
+int gfx_compression_active  = 0;
+int gfx_line_double         = 0;
+int gfx_pixel_double        = 0;
+int gfx_timing_lock         = 0;
+DISPLAYMODE gfx_display_mode;
+
+/* DISPLAY MODE TIMINGS */
+
+DISPLAYMODE DisplayParams[] = {
+
+/* 320 x 200 */
+
+{ GFX_MODE_70HZ |                                   /* refresh rate = 60  */
+  GFX_MODE_8BPP | GFX_MODE_16BPP |					/* 8 and 16 BPP valid */
+  GFX_MODE_NEG_HSYNC |			                    /* negative HSYNC     */
+  GFX_MODE_PIXEL_DOUBLE |                           /* Double width       */
+  GFX_MODE_LINE_DOUBLE,                             /* Double height      */
+  0x140, 0x288, 0x290, 0x2F0, 0x318, 0x320,     	/* horizontal timings */
+  0x0C8, 0x197, 0x19C, 0x19E, 0x1BA, 0x1C1,         /* vertical timings   */
+  0x00192CCC, 										/* freq = 25.175 MHz  */
+},
+
+/* 320 x 240 */
+
+{ GFX_MODE_75HZ |									/* refresh rate = 75  */
+  GFX_MODE_8BPP | GFX_MODE_16BPP |					/* 8 and 16 BPP valid */
+  GFX_MODE_NEG_HSYNC | GFX_MODE_NEG_VSYNC |			/* negative syncs     */
+  GFX_MODE_PIXEL_DOUBLE |                           /* Double width       */
+  GFX_MODE_LINE_DOUBLE,                             /* Double height      */
+  0x0140, 0x0280, 0x0290, 0x02D0, 0x0348, 0x0348,	/* horizontal timings */
+  0x00F0, 0x01E0, 0x01E1, 0x01E4, 0x01F4, 0x01F4,	/* vertical timings   */
+  0x001F8000, 										/* freq = 31.5 MHz    */
+},
+
+/* 400 x 300 */
+
+{ GFX_MODE_75HZ |									/* refresh rate = 75  */
+  GFX_MODE_8BPP | GFX_MODE_16BPP |					/* 8 and 16 BPP valid */
+  GFX_MODE_PIXEL_DOUBLE |                           /* Double width       */
+  GFX_MODE_LINE_DOUBLE,                             /* Double height      */
+  0x0190, 0x0320, 0x0330, 0x0380, 0x0420, 0x0420,   /* horizontal timings */
+  0x012C, 0x0258, 0x0259, 0x025C, 0x0271, 0x0271,	/* vertical timings   */
+  0x00318000, 										/* freq = 49.5 MHz    */
+},
+
+/* 512 x 384 */
+
+{ GFX_MODE_75HZ |									/* refresh rate = 75  */
+  GFX_MODE_8BPP | GFX_MODE_16BPP |					/* 8 and 16 BPP valid */
+  GFX_MODE_PIXEL_DOUBLE |                           /* Double width       */
+  GFX_MODE_LINE_DOUBLE,                             /* Double height      */
+  0x0200, 0x0400, 0x0410, 0x0470, 0x0520, 0x0520,   /* horizontal timings */
+  0x0180, 0x0300, 0x0301, 0x0304, 0x0320, 0x0320,   /* vertical timings   */
+  0x004EC000,									    /* freq = 78.75 MHz   */
+},
+
+/* 640 x 400 */
+
+{ GFX_MODE_70HZ |                                   /* refresh rate = 60  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP |
+  GFX_MODE_NEG_HSYNC,			                    /* negative HSYNC     */
+  0x280, 0x288, 0x290, 0x2F0, 0x318, 0x320,     	/* horizontal timings */
+  0x190, 0x197, 0x19C, 0x19E, 0x1BA, 0x1C1,         /* vertical timings   */
+  0x00192CCC, 										/* freq = 25.175 MHz  */
+},
+
+/* 640x480 */
+
+{ GFX_MODE_60HZ |									/* refresh rate = 60  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP |
+  GFX_MODE_NEG_HSYNC | GFX_MODE_NEG_VSYNC,			/* negative syncs     */
+  0x0280, 0x0288, 0x0290, 0x02E8, 0x0318, 0x0320,	/* horizontal timings */
+  0x01E0, 0x01E8, 0x01EA, 0x01EC, 0x0205, 0x020D,   /* vertical timings   */
+  0x00192CCC, 										/* freq = 25.175 MHz  */
+},
+
+{ GFX_MODE_72HZ |									/* refresh rate = 72  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP |
+  GFX_MODE_NEG_HSYNC | GFX_MODE_NEG_VSYNC,			/* negative syncs     */
+  0x0280, 0x0288, 0x0298, 0x02c0, 0x0338, 0x0340,	/* horizontal timings */
+  0x01e0, 0x01e8, 0x01e9, 0x01ec, 0x0200, 0x0208,   /* vertical timings   */
+  0x001F8000, 										/* freq = 31.5 MHz    */
+},
+
+{ GFX_MODE_75HZ |									/* refresh rate = 75  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP |
+  GFX_MODE_NEG_HSYNC | GFX_MODE_NEG_VSYNC,			/* negative syncs     */
+  0x0280, 0x0280, 0x0290, 0x02D0, 0x0348, 0x0348,	/* horizontal timings */
+  0x01E0, 0x01E0, 0x01E1, 0x01E4, 0x01F4, 0x01F4,	/* vertical timings   */
+  0x001F8000, 										/* freq = 31.5 MHz    */
+},
+
+{ GFX_MODE_85HZ |									/* refresh rate = 85  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP | 
+  GFX_MODE_NEG_HSYNC | GFX_MODE_NEG_VSYNC,			/* negative syncs     */
+  0x0280, 0x0280, 0x02B8, 0x02F0, 0x0340, 0x0340,   /* horizontal timings */
+  0x01E0, 0x01E0, 0x01E1, 0x01E4, 0x01FD, 0x01FD,   /* vertical timings   */
+  0x00240000,  									    /* freq = 36.0 MHz    */
+},
+
+/* 800x600 */
+
+{ GFX_MODE_56HZ |									/* refresh rate = 56  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0320, 0x0328, 0x0348, 0x03D0, 0x0418, 0x0420,	/* horizontal timings */
+  0x0258, 0x0258, 0x0259, 0x025D, 0x0274, 0x0274,   /* vertical timings   */
+  0x00240000, 										/* freq = 36.00 MHz   */
+},
+
+{ GFX_MODE_60HZ |									/* refresh rate = 60  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0320, 0x0328, 0x0348, 0x03D0, 0x0418, 0x0420,	/* horizontal timings */
+  0x0258, 0x0258, 0x0259, 0x025D, 0x0274, 0x0274,   /* vertical timings   */
+  0x00280000, 										/* freq = 40.00 MHz   */
+},
+
+{ GFX_MODE_72HZ |									/* refresh rate = 72  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0320, 0x0320, 0x0358, 0x03D0, 0x0410, 0x0410,   /* horizontal timings */
+  0x0258, 0x0258, 0x027D, 0x0283, 0x029A, 0x029A,	/* vertical timings   */
+  0x00320000, 										/* freq = 49.5 MHz    */
+},
+
+{ GFX_MODE_75HZ |									/* refresh rate = 75  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0320, 0x0320, 0x0330, 0x0380, 0x0420, 0x0420,   /* horizontal timings */
+  0x0258, 0x0258, 0x0259, 0x025C, 0x0271, 0x0271,	/* vertical timings   */
+  0x00318000, 										/* freq = 49.5 MHz    */
+},
+
+{ GFX_MODE_85HZ |									/* refresh rate = 85  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0320, 0x0320, 0x0340, 0x0380, 0x0418, 0x0418,   /* horizontal timings */
+  0x0258, 0x0258, 0x0259, 0x025C, 0x0277, 0x0277,   /* vertical timings   */
+  0x00384000, 									    /* freq = 56.25 MHz   */
+},
+
+/* 1024x768 */
+
+{ GFX_MODE_60HZ |									/* refresh rate = 60  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP |
+  GFX_MODE_NEG_HSYNC | GFX_MODE_NEG_VSYNC,			/* negative syncs     */
+  0x0400, 0x0400, 0x0418, 0x04A0, 0x0540, 0x0540,	/* horizontal timings */
+  0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326,   /* vertical timings   */
+  0x00410000, 									    /* freq = 65.00 MHz   */
+},
+
+{ GFX_MODE_70HZ |									/* refresh rate = 70  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP |
+  GFX_MODE_NEG_HSYNC | GFX_MODE_NEG_VSYNC,			/* negative syncs     */
+  0x0400, 0x0400, 0x0418, 0x04A0, 0x0530, 0x0530,   /* horizontal timings */
+  0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326,   /* vertical timings   */
+  0x004B0000,									    /* freq = 78.75 MHz   */
+},
+
+{ GFX_MODE_75HZ |									/* refresh rate = 75  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0400, 0x0400, 0x0410, 0x0470, 0x0520, 0x0520,   /* horizontal timings */
+  0x0300, 0x0300, 0x0301, 0x0304, 0x0320, 0x0320,   /* vertical timings   */
+  0x004EC000,									    /* freq = 78.75 MHz   */
+},
+
+{ GFX_MODE_85HZ |									/* refresh rate = 85  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0400, 0x0400, 0x0430, 0x0490, 0x0560, 0x0560,   /* horizontal timings */
+  0x0300, 0x0300, 0x0301, 0x0304, 0x0328, 0x0328,   /* vertical timings   */
+  0x005E8000,									    /* freq = 94.50 MHz   */
+},
+
+/* 1152x864 */
+
+{ GFX_MODE_75HZ |									/* refresh rate = 75  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid      */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0480, 0x0480, 0x04C0, 0x0540, 0x0640, 0x0640,   /* horizontal timings */
+  0x0360, 0x0360, 0x0361, 0x0364, 0x0384, 0x0384,   /* vertical timings   */
+  0x006C0000,                                       /* freq = 108.00 MHz  */
+},
+  	
+/* 1280x1024 */
+
+{ GFX_MODE_60HZ |									/* refresh rate = 60  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* Up to 16 bpp       */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0500, 0x0500, 0x0530, 0x05A0, 0x0698, 0x0698,   /* horizontal timings */
+  0x0400, 0x0400, 0x0401, 0x0404, 0x042A, 0x042A,   /* vertical timings   */
+  0x006C0000, 										/* freq = 108.0 MHz   */
+},
+
+{ GFX_MODE_75HZ |									/* refresh rate = 75  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* Up to 16 bpp       */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0500, 0x0500, 0x0510, 0x05A0, 0x0698, 0x0698,   /* horizontal timings */
+  0x0400, 0x0400, 0x0401, 0x0404, 0x042A, 0x042A,   /* vertical timings   */
+  0x00870000, 										/* freq = 135.0 MHz   */
+},
+
+{ GFX_MODE_85HZ |									/* refresh rate = 85  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* Up to 16 bpp       */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0500, 0x0500, 0x0540, 0x05E0, 0x06C0, 0x06C0,   /* horizontal timings */
+  0x0400, 0x0400, 0x0401, 0x0404, 0x0430, 0x0430,   /* vertical timings   */
+  0x009D8000, 									    /* freq = 157.5 MHz   */
+},
+
+/*********************************/
+/* BEGIN REDCLOUD-SPECIFIC MODES */
+/*-------------------------------*/
+
+/* 1600 x 1200 */
+
+{ GFX_MODE_60HZ |                                   /* refresh rate = 60  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* Up to 32 bpp       */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0640, 0x0640, 0x0680, 0x0740, 0x0870, 0x0870,   /* horizontal timings */
+  0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04E2, 0x04E2,   /* vertical timings   */
+  0x00A20000,                                       /* freq = 162.0 MHz   */
+},
+
+{ GFX_MODE_70HZ |                                   /* refresh rate = 70  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* Up to 32 bpp       */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0640, 0x0640, 0x0680, 0x0740, 0x0870, 0x0870,   /* horizontal timings */
+  0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04E2, 0x04E2,   /* vertical timings   */
+  0x00BD0000,                                       /* freq = 189.0 MHz   */
+},
+
+{ GFX_MODE_75HZ |                                   /* refresh rate = 75  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* Up to 32 bpp       */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0640, 0x0640, 0x0680, 0x0740, 0x0870, 0x0870,   /* horizontal timings */
+  0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04E2, 0x04E2,   /* vertical timings   */
+  0x00CA8000,                                       /* freq = 202.5 MHz   */
+},
+
+{ GFX_MODE_85HZ |                                   /* refresh rate = 85  */
+  GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* Up to 32 bpp       */
+  GFX_MODE_16BPP | GFX_MODE_24BPP,
+  0x0640, 0x0640, 0x0680, 0x0740, 0x0870, 0x0870,   /* horizontal timings */
+  0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04E2, 0x04E2,   /* vertical timings   */
+  0x00E58000,                                       /* freq = 229.5 MHz   */
+},
+};
+
+/* UPDATE THIS VARIABLE WHENEVER NEW REDCLOUD-SPECIFIC MODES ARE ADDED */
+
+#define REDCLOUD_SPECIFIC_MODES 4
+
+#define NUM_RC_DISPLAY_MODES sizeof(DisplayParams) / sizeof(DISPLAYMODE)
+#define NUM_GX_DISPLAY_MODES (NUM_RC_DISPLAY_MODES - REDCLOUD_SPECIFIC_MODES)
+
+
+FIXEDTIMINGS FixedParams[] = {
+/* 640x480 Panel */
+{ 640 , 480, 640, 480,									
+  0x0280, 0x0280, 0x0290, 0x02E8, 0x0318, 0x0320,	
+  0x01E0, 0x01E0, 0x01EA, 0x01EC, 0x0205, 0x020D,   
+  0x00192CCC, 										
+},
+
+{ 640 , 480, 800, 600,									
+  0x0280, 0x0280, 0x0290, 0x02E8, 0x0318, 0x0320,	
+  0x01E0, 0x01E0, 0x01EA, 0x01EC, 0x0205, 0x020D,   
+  0x00192CCC, 										
+},
+
+{ 640 , 480, 1024 , 768,									
+  0x0280, 0x0280, 0x0290, 0x02E8, 0x0318, 0x0320,	
+  0x01E0, 0x01E0, 0x01EA, 0x01EC, 0x0205, 0x020D,   
+  0x00192CCC, 										
+},
+
+{ 640 , 480, 1152 , 864,									
+  0x0280, 0x0280, 0x0290, 0x02E8, 0x0318, 0x0320,	
+  0x01E0, 0x01E0, 0x01EA, 0x01EC, 0x0205, 0x020D,   
+  0x00192CCC, 										
+},
+
+{ 640 , 480, 1280, 1024,									
+  0x0280, 0x0280, 0x0290, 0x02E8, 0x0318, 0x0320,	
+  0x01E0, 0x01E0, 0x01EA, 0x01EC, 0x0205, 0x020D,   
+  0x00192CCC, 										
+},
+
+{ 640 , 480, 1600, 1200,									
+  0x0280, 0x0280, 0x0290, 0x02E8, 0x0318, 0x0320,	
+  0x01E0, 0x01E0, 0x01EA, 0x01EC, 0x0205, 0x020D,   
+  0x00192CCC, 										
+},
+
+
+/* 800x600 Panel */
+{ 800 , 600, 640, 480,									
+  0x0280, 0x2d0, 0x2f8, 0x378, 0x3d0, 0x420,	
+  0x1e0, 0x21c, 0x21d, 0x221, 0x238, 0x274,   
+  0x00280000, 										
+},
+
+{ 800 , 600, 800, 600,									
+  0x320, 0x320, 0x348, 0x3c8, 0x420, 0x420,	
+  0x258, 0x258, 0x259, 0x25d, 0x274, 0x274,   
+  0x00280000, 										
+},
+
+{ 800 , 600, 1024, 768,									
+  0x320, 0x320, 0x348, 0x3c8, 0x420, 0x420,	
+  0x258, 0x258, 0x259, 0x25d, 0x274, 0x274,   
+  0x00280000, 										
+},
+
+{ 800 , 600, 1152, 864,									
+  0x320, 0x320, 0x348, 0x3c8, 0x420, 0x420,	
+  0x258, 0x258, 0x259, 0x25d, 0x274, 0x274,   
+  0x00280000, 										
+},
+
+{ 800 , 600, 1280, 1024,									
+  0x320, 0x320, 0x348, 0x3c8, 0x420, 0x420,	
+  0x258, 0x258, 0x259, 0x25d, 0x274, 0x274,   
+  0x00280000, 										
+},
+
+{ 800 , 600, 1600, 1200,									
+  0x320, 0x320, 0x348, 0x3c8, 0x420, 0x420,	
+  0x258, 0x258, 0x259, 0x25d, 0x274, 0x274,   
+  0x00280000, 										
+},
+
+/* 1024x768 panel */
+{ 1024 , 768, 640, 480,									
+  0x0280, 0x340, 0x368, 0x3e8, 0x480, 0x540,	
+  0x1e0, 0x270, 0x271, 0x275, 0x296, 0x326,   
+  0x00410000, 										
+},
+
+{ 1024 , 768, 800, 600,									
+  0x0320, 0x390, 0x3b8, 0x438, 0x4D0, 0x540,	
+  0x258, 0x2ac, 0x2ad, 0x2b1, 0x2D2, 0x326,   
+  0x00410000, 										
+},
+
+{ 1024 , 768, 1024, 768,									
+  0x0400, 0x0400, 0x0418, 0x04A0, 0x0540, 0x0540,	
+  0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326,   
+  0x00410000, 										
+},
+
+
+{ 1024 , 768, 1152, 864,									
+  0x0400, 0x0400, 0x0418, 0x04A0, 0x0540, 0x0540,	
+  0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326,   
+  0x00410000, 										
+},
+
+{ 1024 , 768, 1280, 1024,									
+  0x0400, 0x0400, 0x0418, 0x04A0, 0x0540, 0x0540,	
+  0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326,   
+  0x00410000, 										
+},
+
+{ 1024 , 768, 1600, 1200,									
+  0x0400, 0x0400, 0x0418, 0x04A0, 0x0540, 0x0540,	
+  0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326,   
+  0x00410000, 										
+},
+
+};
+
+
+#define NUM_FIXED_TIMINGS_MODES sizeof(FixedParams)/sizeof(FIXEDTIMINGS)
+
+
+/* INCLUDE SUPPORT FOR FIRST GENERATION, IF SPECIFIED. */
+
+#if GFX_DISPLAY_GU1
+#include "disp_gu1.c"
+#endif
+
+/* INCLUDE SUPPORT FOR SECOND GENERATION, IF SPECIFIED. */
+
+#if GFX_DISPLAY_GU2
+#include "disp_gu2.c"
+#endif
+
+/*---------------------------------------------------------------------------
+ * gfx_reset_timing_lock
+ * 
+ * This routine resets the timing change lock. The lock can only be set by
+ * setting a flag when calling mode set.
+ *---------------------------------------------------------------------------
+ */
+void gfx_reset_timing_lock(void)
+{
+	gfx_timing_lock = 0;
+}
+
+/* WRAPPERS IF DYNAMIC SELECTION */
+/* Extra layer to call either first or second generation routines. */
+
+#if GFX_DISPLAY_DYNAMIC
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_bpp
+ *---------------------------------------------------------------------------
+ */
+int gfx_set_display_bpp(unsigned short bpp)
+{
+	int retval = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		retval = gu1_set_display_bpp(bpp);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		retval = gu2_set_display_bpp(bpp);
+#endif
+	return(retval);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_is_display_mode_supported
+ * check if given mode supported, 
+ * return the supported mode on success, -1 on fail
+ *---------------------------------------------------------------------------
+ */
+int gfx_is_display_mode_supported(int xres, int yres, int bpp, int hz)
+{
+	int retval = -1;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		retval = gu1_is_display_mode_supported(xres, yres, bpp, hz);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		retval = gu2_is_display_mode_supported(xres, yres, bpp, hz);
+#endif
+	return(retval);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_mode
+ *---------------------------------------------------------------------------
+ */
+int gfx_set_display_mode(int xres, int yres, int bpp, int hz)
+{
+	int retval = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		retval = gu1_set_display_mode(xres, yres, bpp, hz);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		retval = gu2_set_display_mode(xres, yres, bpp, hz);
+#endif
+	return(retval);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_timings
+ *---------------------------------------------------------------------------
+ */
+int gfx_set_display_timings(unsigned short bpp, unsigned short flags, 
+	unsigned short hactive, unsigned short hblankstart, 
+	unsigned short hsyncstart, unsigned short hsyncend,
+	unsigned short hblankend, unsigned short htotal,
+	unsigned short vactive, unsigned short vblankstart, 
+	unsigned short vsyncstart, unsigned short vsyncend,
+	unsigned short vblankend, unsigned short vtotal,
+	unsigned long frequency)
+{
+	int retval = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		retval = gu1_set_display_timings(bpp, flags, 
+			hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal,
+			vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal,
+			frequency);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		retval = gu2_set_display_timings(bpp, flags, 
+			hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal,
+			vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal,
+			frequency);
+#endif
+	return(retval);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_pitch
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_display_pitch(unsigned short pitch)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_set_display_pitch(pitch);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_display_pitch(pitch);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_offset
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_display_offset(unsigned long offset)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_set_display_offset(offset);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_display_offset(offset);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_palette_entry
+ *---------------------------------------------------------------------------
+ */
+int gfx_set_display_palette_entry(unsigned long index, unsigned long palette)
+{
+	int status = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		status = gu1_set_display_palette_entry(index, palette);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		status = gu2_set_display_palette_entry(index, palette);
+#endif
+	return(status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_palette
+ *---------------------------------------------------------------------------
+ */
+int gfx_set_display_palette(unsigned long *palette)
+{
+	int status = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		status = gu1_set_display_palette(palette);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		status = gu2_set_display_palette(palette);
+#endif
+	return(status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_cursor_enable
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_cursor_enable(int enable)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_set_cursor_enable(enable);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_cursor_enable(enable);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_cursor_colors
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_set_cursor_colors(bkcolor, fgcolor);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_cursor_colors(bkcolor, fgcolor);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_cursor_position
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_cursor_position(unsigned long memoffset, 
+	unsigned short xpos, unsigned short ypos, 
+	unsigned short xhotspot, unsigned short yhotspot)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_set_cursor_position(memoffset, xpos, ypos, xhotspot, yhotspot);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_cursor_position(memoffset, xpos, ypos, xhotspot, yhotspot);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_cursor_shape32
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_cursor_shape32(unsigned long memoffset, 
+	unsigned long *andmask, unsigned long *xormask)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_set_cursor_shape32(memoffset, andmask, xormask);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_cursor_shape32(memoffset, andmask, xormask);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_cursor_shape64
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_cursor_shape64(unsigned long memoffset, 
+	unsigned long *andmask, unsigned long *xormask)
+{
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_cursor_shape64(memoffset, andmask, xormask);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_icon_enable
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_icon_enable(int enable)
+{
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_icon_enable(enable);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_icon_colors
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_icon_colors (unsigned long color0, unsigned long color1, unsigned long color2)
+{
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_icon_colors (color0, color1, color2);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_icon_position
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_icon_position(unsigned long memoffset, unsigned short xpos)
+{
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_icon_position(memoffset, xpos);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_icon_shape64
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_icon_shape64(unsigned long memoffset, 
+	unsigned long *andmask, unsigned long *xormask, unsigned int lines)
+{
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_icon_shape64(memoffset, andmask, xormask, lines);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_compression_enable
+ *---------------------------------------------------------------------------
+ */
+int gfx_set_compression_enable(int enable)
+{
+	int status = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		status = gu1_set_compression_enable(enable);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		status = gu2_set_compression_enable(enable);
+#endif
+	return(status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_compression_offset
+ *---------------------------------------------------------------------------
+ */
+int gfx_set_compression_offset(unsigned long offset)
+{
+	int status = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		status = gu1_set_compression_offset(offset);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		status = gu2_set_compression_offset(offset);
+#endif
+	return(status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_compression_pitch
+ *---------------------------------------------------------------------------
+ */
+int gfx_set_compression_pitch(unsigned short pitch)
+{
+	int status = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		status = gu1_set_compression_pitch(pitch);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		status = gu2_set_compression_pitch(pitch);
+#endif
+	return(status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_compression_size
+ *---------------------------------------------------------------------------
+ */
+int gfx_set_compression_size(unsigned short size)
+{
+	int status = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		status = gu1_set_compression_size(size);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		status = gu2_set_compression_size(size);
+#endif
+	return(status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_priority_high
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_display_priority_high(int enable)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_set_display_priority_high(enable);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_format (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_format".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_display_video_format(unsigned long format)
+{
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_display_video_format(format);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_enable (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_enable".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_display_video_enable(int enable)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_set_display_video_enable(enable);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_display_video_enable(enable);
+#endif
+	return;
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_size (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_size".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_display_video_size(unsigned short width, unsigned short height)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_set_display_video_size(width, height);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_display_video_size(width, height);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_offset (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_offset".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_display_video_offset(unsigned long offset)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_set_display_video_offset(offset);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_display_video_offset(offset);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_yuv_offsets (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_yuv_offsets".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_display_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset,
+									   unsigned long voffset)
+{
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_display_video_yuv_offsets(yoffset, uoffset, voffset);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_yuv_pitch (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_yuv_pitch".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_display_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch)
+{
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_display_video_yuv_pitch (ypitch, uvpitch);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_downscale (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_vertical_downscale".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_display_video_downscale (unsigned short srch, unsigned short dsth)
+{
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_display_video_downscale (srch, dsth);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_display_video_vertical_downscale_enable (PRIVATE ROUTINE - NOT PART OF API)
+ *
+ * This routine is called by "gfx_set_video_vertical_downscale_enable".  It abstracts the 
+ * version of the display controller from the video overlay routines.
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_display_video_vertical_downscale_enable (int enable)
+{
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_set_display_video_vertical_downscale_enable (enable);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_test_timing_active
+ *---------------------------------------------------------------------------
+ */
+int gfx_test_timing_active(void)
+{
+	int status = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		status = gu1_test_timing_active();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		status = gu2_test_timing_active();
+#endif
+	return(status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_test_vertical_active
+ *---------------------------------------------------------------------------
+ */
+int gfx_test_vertical_active(void)
+{
+	int status = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		status = gu1_test_vertical_active();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		status = gu2_test_vertical_active();
+#endif
+	return(status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_wait_vertical_blank
+ *---------------------------------------------------------------------------
+ */
+int gfx_wait_vertical_blank(void)
+{
+	int status = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		status = gu1_wait_vertical_blank();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		status = gu2_wait_vertical_blank();
+#endif
+	return(status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_delay_milliseconds
+ *---------------------------------------------------------------------------
+ */
+void gfx_delay_milliseconds(unsigned long milliseconds)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_delay_milliseconds(milliseconds);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_delay_milliseconds(milliseconds);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_delay_microseconds
+ *---------------------------------------------------------------------------
+ */
+void gfx_delay_microseconds(unsigned long microseconds)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_delay_microseconds(microseconds);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_delay_microseconds(microseconds);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_enable_panning 
+ *
+ * This routine  enables the panning when the Mode is bigger than the panel
+ * size.
+ *---------------------------------------------------------------------------
+ */
+void gfx_enable_panning(int x, int y)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_enable_panning( x,  y);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_enable_panning( x,  y);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_fixed_timings
+ *---------------------------------------------------------------------------
+ */
+int gfx_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp)
+{
+	int status = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		status = gu1_set_fixed_timings( panelResX,  panelResY,   width,   height,  bpp);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		status = gu2_set_fixed_timings( panelResX,  panelResY,   width,   height,  bpp);
+#endif
+	return (status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_panel_present
+ *---------------------------------------------------------------------------
+ */
+int gfx_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp)
+{
+	int status = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		status = gu1_set_panel_present( panelResX,  panelResY,   width,   height,  bpp);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		status = gu2_set_panel_present( panelResX,  panelResY,   width,   height,  bpp);
+#endif
+	return (status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_vtotal
+ *---------------------------------------------------------------------------
+ */
+int gfx_set_vtotal(unsigned short vtotal)
+{
+	int retval = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		retval = gu1_set_vtotal(vtotal);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		retval = gu2_set_vtotal(vtotal);
+#endif
+	return(retval);
+}
+
+/*-----------------------------------------------------------------------*
+ * THE FOLLOWING READ ROUTINES ARE ALWAYS INCLUDED:                      *                      
+ * gfx_get_hsync_end, gfx_get_htotal, gfx_get_vsync_end, gfx_get_vtotal  *
+ * are used by the video overlay routines.                               *
+ *                                                                       *
+ * gfx_get_vline and gfx_vactive are used to prevent an issue for the    *
+ * SC1200.                                                               *
+ *                                                                       *
+ * The others are part of the Durango API.                               *
+ *-----------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ * gfx_mode_frequency_supported
+ *----------------------------------------------------------------------------  
+ */
+int gfx_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency)
+{
+	int freq = 0;
+
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		freq = gu1_mode_frequency_supported(xres, yres, bpp, frequency);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		freq = gu2_mode_frequency_supported(xres, yres, bpp, frequency);
+#endif
+	return(freq);
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_refreshrate_from_frequency
+ *----------------------------------------------------------------------------  
+ */
+int gfx_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_get_refreshrate_from_frequency(xres, yres, bpp, hz, frequency);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_get_refreshrate_from_frequency(xres, yres, bpp, hz, frequency);
+#endif
+
+	return(1);
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_refreshrate_from_mode
+ *----------------------------------------------------------------------------  
+ */
+int gfx_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_get_refreshrate_from_mode(xres, yres, bpp, hz, frequency);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_get_refreshrate_from_mode(xres, yres, bpp, hz, frequency);
+#endif
+
+	return(1);
+}
+
+/*----------------------------------------------------------------------------
+ * gfx_get_frequency_from_refreshrate
+ *----------------------------------------------------------------------------  
+ */
+int gfx_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency)
+{
+	int retval = -1;
+
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		retval = gu1_get_frequency_from_refreshrate(xres, yres, bpp, hz, frequency);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		retval = gu2_get_frequency_from_refreshrate(xres, yres, bpp, hz, frequency);
+#endif
+
+	return retval;
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_max_supported_pixel_clock
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_max_supported_pixel_clock (void)
+{
+	unsigned long status = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		status = gu1_get_max_supported_pixel_clock();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		status = gu2_get_max_supported_pixel_clock();
+#endif
+	return (status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_pitch
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_display_pitch(void)
+{
+	unsigned short pitch = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		pitch = gu1_get_display_pitch();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		pitch = gu2_get_display_pitch();
+#endif
+	return(pitch);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_mode_count 
+ * return # of modes supported.
+ *---------------------------------------------------------------------------
+ */
+int gfx_get_display_mode_count(void)
+{
+	int retval = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		retval = gu1_get_display_mode_count();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		retval = gu2_get_display_mode_count();
+#endif
+	return(retval);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_frame_buffer_line_size
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_frame_buffer_line_size(void)
+{
+	unsigned long retval = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		retval = gu1_get_frame_buffer_line_size();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		retval = gu2_get_frame_buffer_line_size();
+#endif
+	return(retval);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_mode
+ * get the curent mode set, 
+ * return the supported mode on success, -1 on fail
+ *---------------------------------------------------------------------------
+ */
+int gfx_get_display_mode(int *xres, int *yres, int *bpp, int *hz)
+{
+	int retval = -1;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		retval = gu1_get_display_mode(xres, yres, bpp, hz);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		retval = gu2_get_display_mode(xres, yres, bpp, hz);
+#endif
+	return(retval);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_details
+ * given the mode get's the resoultion details, width, height, freq
+ *---------------------------------------------------------------------------
+ */
+int gfx_get_display_details(unsigned int mode, int *xres, int *yres, int *hz)
+{
+	int retval = -1;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		retval = gu1_get_display_details(mode, xres, yres, hz);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		retval = gu2_get_display_details(mode, xres, yres, hz);
+#endif
+	return(retval);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hactive
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_hactive(void)
+{
+	unsigned short hactive = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		hactive = gu1_get_hactive();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		hactive = gu2_get_hactive();
+#endif
+	return(hactive);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hsync_start
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_hsync_start(void)
+{
+	unsigned short hsync_start = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		hsync_start = gu1_get_hsync_start();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		hsync_start = gu2_get_hsync_start();
+#endif
+	return(hsync_start);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hsync_end
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_hsync_end(void)
+{
+	unsigned short hsync_end = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		hsync_end = gu1_get_hsync_end();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		hsync_end = gu2_get_hsync_end();
+#endif
+	return(hsync_end);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_htotal
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_htotal(void)
+{
+	unsigned short htotal = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		htotal = gu1_get_htotal();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		htotal = gu2_get_htotal();
+#endif
+	return(htotal);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vactive
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_vactive(void)
+{
+	unsigned short vactive = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		vactive = gu1_get_vactive();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		vactive = gu2_get_vactive();
+#endif
+	return(vactive);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vsync_end
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_vsync_end(void)
+{
+	unsigned short vsync_end = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		vsync_end = gu1_get_vsync_end();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		vsync_end = gu2_get_vsync_end();
+#endif
+	return(vsync_end);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vtotal
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_vtotal(void)
+{
+	unsigned short vtotal = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		vtotal = gu1_get_vtotal();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		vtotal = gu2_get_vtotal();
+#endif
+	return(vtotal);
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_display_bpp
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_display_bpp(void)
+{
+	unsigned short bpp = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		bpp = gu1_get_display_bpp();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		bpp = gu2_get_display_bpp();
+#endif
+	return(bpp);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vline
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_vline(void)
+{
+	unsigned short vline = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		vline = gu1_get_vline();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		vline = gu2_get_vline();
+#endif
+	return(vline);
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_display_offset
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_display_offset(void)
+{
+	unsigned long offset = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		offset = gu1_get_display_offset();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		offset = gu2_get_display_offset();
+#endif
+	return(offset);
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_cursor_offset
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_cursor_offset(void)
+{
+	unsigned long base = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		base = gu1_get_cursor_offset();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		base = gu2_get_cursor_offset();
+#endif
+	return(base);
+}
+
+/*************************************************************/
+/*  READ ROUTINES  |  INCLUDED FOR DIAGNOSTIC PURPOSES ONLY  */
+/*************************************************************/
+
+#if GFX_READ_ROUTINES
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hblank_start
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_hblank_start(void)
+{
+	unsigned short hblank_start = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		hblank_start = gu1_get_hblank_start();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		hblank_start = gu2_get_hblank_start();
+#endif
+	return(hblank_start);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_hblank_end
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_hblank_end(void)
+{
+	unsigned short hblank_end = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		hblank_end = gu1_get_hblank_end();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		hblank_end = gu2_get_hblank_end();
+#endif
+	return(hblank_end);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vblank_start
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_vblank_start(void)
+{
+	unsigned short vblank_start = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		vblank_start = gu1_get_vblank_start();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		vblank_start = gu2_get_vblank_start();
+#endif
+	return(vblank_start);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vsync_start
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_vsync_start(void)
+{
+	unsigned short vsync_start = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		vsync_start = gu1_get_vsync_start();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		vsync_start = gu2_get_vsync_start();
+#endif
+	return(vsync_start);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_vblank_end
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_vblank_end(void)
+{
+	unsigned short vblank_end = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		vblank_end = gu1_get_vblank_end();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		vblank_end = gu2_get_vblank_end();
+#endif
+	return(vblank_end);
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_display_palette_entry
+ *---------------------------------------------------------------------------
+ */
+int gfx_get_display_palette_entry(unsigned long index, unsigned long *palette)
+{
+	int status = 0;
+
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		status = gu1_get_display_palette_entry(index, palette);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		status = gu2_get_display_palette_entry(index, palette);
+#endif
+
+	return status;
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_display_palette
+ *---------------------------------------------------------------------------
+ */
+void gfx_get_display_palette(unsigned long *palette)
+{
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		gu1_get_display_palette(palette);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_get_display_palette(palette);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_cursor_enable
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_cursor_enable(void)
+{
+	unsigned long enable = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		enable = gu1_get_cursor_enable();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		enable = gu2_get_cursor_enable();
+#endif
+	return(enable);
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_cursor_position
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_cursor_position(void)
+{
+	unsigned long position = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		position = gu1_get_cursor_position();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		position = gu2_get_cursor_position();
+#endif
+	return(position);
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_cursor_clip
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_cursor_clip(void)
+{
+	unsigned long offset = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		offset = gu1_get_cursor_clip();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		offset = gu2_get_cursor_clip();
+#endif
+	return(offset);
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_cursor_color
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_cursor_color(int index)
+{
+	unsigned long color = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		color = gu1_get_cursor_color(index);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		color = gu2_get_cursor_color(index);
+#endif
+	return(color);
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_icon_enable
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_icon_enable(void)
+{
+	unsigned long enable = 0;
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		enable = gu2_get_icon_enable();
+#endif
+	return(enable);
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_icon_offset
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_icon_offset(void)
+{
+	unsigned long base = 0;
+	
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		base = gu2_get_icon_offset();
+#endif
+	
+	return(base);
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_icon_position
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_icon_position(void)
+{
+	unsigned long position = 0;
+	
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		position = gu2_get_icon_position();
+#endif
+	
+	return(position);
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_icon_color
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_icon_color(int index)
+{
+	unsigned long color = 0;
+
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		color = gu2_get_icon_color(index);
+#endif
+	
+	return(color);
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_compression_enable
+ *---------------------------------------------------------------------------
+ */
+int gfx_get_compression_enable(void)
+{
+	int enable = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		enable = gu1_get_compression_enable();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		enable = gu2_get_compression_enable();
+#endif
+	return(enable);
+}
+
+/*---------------------------------------------------------------------------
+ *  gfx_get_compression_offset
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_compression_offset(void)
+{
+	unsigned long offset = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		offset = gu1_get_compression_offset();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		offset = gu2_get_compression_offset();
+#endif
+	return(offset);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_compression_pitch
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_compression_pitch(void)
+{
+	unsigned short pitch = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		pitch = gu1_get_compression_pitch();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		pitch = gu2_get_compression_pitch();
+#endif
+	return(pitch);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_compression_size
+ *---------------------------------------------------------------------------
+ */
+unsigned short gfx_get_compression_size(void)
+{
+	unsigned short size = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		size = gu1_get_compression_size();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		size = gu2_get_compression_size();
+#endif
+	return(size);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_priority_high
+ *---------------------------------------------------------------------------
+ */
+int gfx_get_display_priority_high(void)
+{
+	int high = GFX_STATUS_UNSUPPORTED;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		high = gu1_get_display_priority_high();
+#endif
+	return(high);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_valid_bit
+ *---------------------------------------------------------------------------
+ */
+int gfx_get_valid_bit(int line)
+{
+	int valid = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		valid = gu1_get_valid_bit(line);
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		valid = gu2_get_valid_bit(line);
+#endif
+	return(valid);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_video_offset
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_display_video_offset(void)
+{
+	unsigned long offset = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		offset = gu1_get_display_video_offset();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		offset = gu2_get_display_video_offset();
+#endif
+	return(offset);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_video_yuv_offsets
+ *---------------------------------------------------------------------------
+ */
+void gfx_get_display_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset,
+												unsigned long *voffset)
+{
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_get_display_video_yuv_offsets(yoffset, uoffset, voffset);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_video_yuv_offsets
+ *---------------------------------------------------------------------------
+ */
+void gfx_get_display_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch)
+{
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		gu2_get_display_video_yuv_pitch(ypitch, uvpitch);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_video_downscale_delta
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_display_video_downscale_delta(void)
+{
+	unsigned long ret_value = 0;
+
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		ret_value = gu2_get_display_video_downscale_delta();
+#endif
+
+	return ret_value;
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_video_downscale_delta
+ *---------------------------------------------------------------------------
+ */
+int gfx_get_display_video_downscale_enable(void)
+{
+	int ret_value = 0;
+
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		ret_value = gu2_get_display_video_downscale_enable();
+#endif
+
+	return ret_value;
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_get_display_video_size
+ *---------------------------------------------------------------------------
+ */
+unsigned long gfx_get_display_video_size(void)
+{
+	unsigned long size = 0;
+#if GFX_DISPLAY_GU1
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU1)
+		size = gu1_get_display_video_size();
+#endif
+#if GFX_DISPLAY_GU2
+	if (gfx_display_type & GFX_DISPLAY_TYPE_GU2)
+		size = gu2_get_display_video_size();
+#endif
+	return(size);
+}
+
+#endif /* GFX_READ_ROUTINES */
+
+#endif /* GFX_DISPLAY_DYNAMIC */
+
+/* END OF FILE */
diff -uNr linux-2.4.31/drivers/video/nsc/gfx/gfx_i2c.c linux-fb/drivers/video/nsc/gfx/gfx_i2c.c
--- linux-2.4.31/drivers/video/nsc/gfx/gfx_i2c.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/gfx/gfx_i2c.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,157 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * This file contains routines to write to and read from the I2C bus.
+ * </DOC_AMD_STD>
+ */
+
+/* INCLUDE ROUTINES FOR ACCESS.BUS, IF SPECIFIED */
+/* This is for SC1200 systems. */
+
+#if GFX_I2C_ACCESS
+#include "i2c_acc.c"
+#endif
+
+/* INCLUDE ROUTINES FOR CS5530 GPIOs, IF SPECIFIED */
+/* This is for GXLV systems that use GPIOs on the CS5530 for I2C. */
+
+#if GFX_I2C_GPIO
+#include "i2c_gpio.c"
+#endif
+
+/* WRAPPERS IF DYNAMIC SELECTION */
+/* Extra layer to call either ACCESS.bus or GPIO routines. */
+
+#if GFX_I2C_DYNAMIC
+
+/*---------------------------------------------------------------------------
+ * gfx_i2c_reset
+ *---------------------------------------------------------------------------
+ */
+int gfx_i2c_reset(unsigned char busnum, short adr, char freq)
+{
+	int status = GFX_STATUS_UNSUPPORTED;
+#if GFX_I2C_ACCESS
+	if (gfx_i2c_type & GFX_I2C_TYPE_ACCESS)
+		status = acc_i2c_reset(busnum, adr, freq);
+#endif
+#if GFX_I2C_GPIO
+	if (gfx_i2c_type & GFX_I2C_TYPE_GPIO)
+		status = gpio_i2c_reset(busnum, adr, freq);
+#endif
+	return(status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_i2c_select_gpio
+ *---------------------------------------------------------------------------
+ */
+int gfx_i2c_select_gpio(int clock, int data)
+{
+#if GFX_I2C_ACCESS
+	if (gfx_i2c_type & GFX_I2C_TYPE_ACCESS)
+		acc_i2c_select_gpio(clock, data);
+#endif
+#if GFX_I2C_GPIO
+	if (gfx_i2c_type & GFX_I2C_TYPE_GPIO)
+		gpio_i2c_select_gpio(clock, data);
+#endif
+	return(0);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_i2c_write
+ *---------------------------------------------------------------------------
+ */
+int gfx_i2c_write(unsigned char busnum, unsigned char chipadr, unsigned char subadr, 
+	unsigned char bytes, unsigned char * data)
+{
+	int status = -1;
+#if GFX_I2C_ACCESS
+	if (gfx_i2c_type & GFX_I2C_TYPE_ACCESS)
+		status = acc_i2c_write(busnum, chipadr, subadr, bytes, data);
+#endif
+#if GFX_I2C_GPIO
+	if (gfx_i2c_type & GFX_I2C_TYPE_GPIO)
+		status = gpio_i2c_write(busnum, chipadr, subadr, bytes, data);
+#endif
+	return(status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_i2c_read
+ *---------------------------------------------------------------------------
+ */
+int gfx_i2c_read(unsigned char busnum, unsigned char chipadr, unsigned char subadr, 
+	unsigned char bytes, unsigned char * data)
+{
+	int status = -1;
+#if GFX_I2C_ACCESS
+	if (gfx_i2c_type & GFX_I2C_TYPE_ACCESS)
+		status = acc_i2c_read(busnum, chipadr, subadr, bytes, data);
+#endif
+#if GFX_I2C_GPIO
+	if (gfx_i2c_type & GFX_I2C_TYPE_GPIO)
+		status = gpio_i2c_read(busnum, chipadr, subadr, bytes, data);
+#endif
+	return(status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_i2c_init
+ *---------------------------------------------------------------------------
+ */
+int gfx_i2c_init(void)
+{
+	int status = -1;
+#if GFX_I2C_ACCESS
+	if (gfx_i2c_type & GFX_I2C_TYPE_ACCESS)
+		status = acc_i2c_init();
+#endif
+#if GFX_I2C_GPIO
+	if (gfx_i2c_type & GFX_I2C_TYPE_GPIO)
+		status = gpio_i2c_init();
+#endif
+	return(status);
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_i2c_cleanup
+ *---------------------------------------------------------------------------
+ */
+void gfx_i2c_cleanup(void)
+{
+#if GFX_I2C_ACCESS
+	if (gfx_i2c_type & GFX_I2C_TYPE_ACCESS)
+		acc_i2c_cleanup();
+#endif
+#if GFX_I2C_GPIO
+	if (gfx_i2c_type & GFX_I2C_TYPE_GPIO)
+		gpio_i2c_cleanup();
+#endif
+}
+
+#endif /* GFX_I2C_DYNAMIC */
+	
+/* END OF FILE */
diff -uNr linux-2.4.31/drivers/video/nsc/gfx/gfx_init.c linux-fb/drivers/video/nsc/gfx/gfx_init.c
--- linux-2.4.31/drivers/video/nsc/gfx/gfx_init.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/gfx/gfx_init.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,599 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * This file contains routines typically used in driver initialization.
+ *
+ * Routines:
+ * 
+ *       gfx_pci_config_read
+ *       gfx_cpu_config_read
+ *       gfx_detect_cpu
+ *       gfx_detect_video
+ *       gfx_get_cpu_register_base
+ *       gfx_get_frame_buffer_base
+ *       gfx_get_frame_buffer_size
+ *       gfx_get_vid_register_base
+ *       gfx_get_vip_register_base
+ * </DOC_AMD_STD>
+ */
+
+
+/* CONSTANTS USED BY THE INITIALIZATION CODE */
+
+#define PCI_CONFIG_ADDR			         0x0CF8
+#define PCI_CONFIG_DATA			         0x0CFC
+#define PCI_VENDOR_DEVICE_GXM	         0x00011078
+#define PCI_VENDOR_DEVICE_REDCLOUD       0x0028100B
+#define REDCLOUD_VIDEO_PCI_VENDOR_DEVICE 0x0030100B
+
+#define GXM_CONFIG_GCR			0xB8
+#define GXM_CONFIG_CCR3			0xC3
+#define GXM_CONFIG_DIR0			0xFE
+#define GXM_CONFIG_DIR1			0xFF
+
+/* STATIC VARIABLES FOR THIS FILE */
+
+unsigned long gfx_cpu_version   = 0;
+unsigned long gfx_cpu_frequency = 0;
+unsigned long gfx_vid_version   = 0;
+unsigned long gfx_gx1_scratch_base = 0;
+unsigned long gfx_gx2_scratch_base = 0x7FC000;
+ChipType gfx_chip_revision = CHIP_NOT_DETECTED;
+
+ChipType gfx_detect_chip(void);
+
+/* INCLUDE SUPPORT FOR FIRST GENERATION, IF SPECIFIED. */
+
+#if GFX_INIT_GU1
+#include "init_gu1.c"
+#endif
+
+/* INCLUDE SUPPORT FOR SECOND GENERATION, IF SPECIFIED. */
+
+#if GFX_INIT_GU2
+#include "init_gu2.c"
+#endif
+
+/* THE FOLLOWING ROUTINES ARE NEVER DYNAMIC              */
+/* They are used to set the variables for future dynamic */
+/* function calls.                                       */
+
+/*-----------------------------------------------------------------------------
+ * gfx_detect_chip
+ *
+ * This routine returns the name and revision of the chip. This function is only
+ * relevant to the SC1200.
+ *-----------------------------------------------------------------------------
+ */
+ChipType gfx_detect_chip(void)
+{
+	unsigned char pid = INB(SC1200_CB_BASE_ADDR + SC1200_CB_PID);
+	unsigned char rev = INB(SC1200_CB_BASE_ADDR + SC1200_CB_REV);
+
+	gfx_chip_revision = CHIP_NOT_DETECTED;
+
+	if (pid == 0x4)
+	{
+		switch (rev)
+		{
+			case 0:
+				gfx_chip_revision = SC1200_REV_A;
+				break;
+			case 1:
+				gfx_chip_revision = SC1200_REV_B1_B2;
+				break;
+			case 2:
+				gfx_chip_revision = SC1200_REV_B3;
+				break;
+			case 3:
+				gfx_chip_revision = SC1200_REV_C1;
+				break;
+			case 4:
+				gfx_chip_revision = SC1200_REV_D1;
+				break;
+			case 5:
+				gfx_chip_revision = SC1200_REV_D1_1;
+				break;
+			case 6:
+				gfx_chip_revision = SC1200_REV_D2_MVD;
+				break;
+		}
+		if (rev > 0x6)
+			gfx_chip_revision = SC1200_FUTURE_REV;
+	}
+	else if (pid == 0x5)
+	{
+		if (rev == 0x6)
+			gfx_chip_revision = SC1200_REV_D2_MVE;
+		else if (rev > 0x6)
+			gfx_chip_revision = SC1200_FUTURE_REV;
+	}
+	return(gfx_chip_revision);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_detect_cpu
+ * 
+ * This routine returns the type and revison of the CPU.  If a Geode 
+ * processor is not present, the routine returns zero.
+ *
+ * The return value is as follows:
+ *     bits[24:16] = minor version
+ *     bits[15:8] = major version 
+ *     bits[7:0] = type (1 = GXm, 2 = SC1200, 3 = Redcloud)
+ *
+ * A return value of 0x00020501, for example, indicates GXm version 5.2.
+ *-----------------------------------------------------------------------------
+ */
+unsigned long gfx_detect_cpu(void)
+{
+	
+	unsigned long value = 0;
+	unsigned long version = 0;
+
+	/* initialize core freq. to 0 */
+	gfx_cpu_frequency = 0;
+		
+#if	GFX_INIT_GU1
+
+	value = gfx_pci_config_read(0x80000000);
+	
+	if (value == PCI_VENDOR_DEVICE_GXM)
+	{	
+		unsigned char dir0 = gfx_gxm_config_read(GXM_CONFIG_DIR0) & 0xF0;
+		unsigned char dir1 = gfx_gxm_config_read(GXM_CONFIG_DIR1);
+
+		if (dir0 == 0x40)
+		{
+			/* CHECK FOR GXLV (and GXm) (DIR1 = 0x30 THROUGH 0x82) */
+
+			if ((dir1 >= 0x30) && (dir1 <= 0x82))
+			{
+				/* Major version is one less than what appears in DIR1 */
+				if( (dir1&0xF0)<0x70){
+
+					version = GFX_CPU_GXLV | 
+
+						((( ( (unsigned long) dir1 >> 4)-1 ) << 8) )  | /* major - 1 */
+					
+						((((unsigned long) dir1 & 0x0F)) << 16);		/* minor */
+				}
+				else{
+					version = GFX_CPU_GXLV | 
+						((((unsigned long) dir1 >> 4) )  << 8) | /* major */
+						((((unsigned long) dir1 & 0x0F)) << 16); /* minor */
+	
+				}
+				/* Currently always CS5530 for video overlay. */
+
+#if GFX_VIDEO_DYNAMIC
+				gfx_video_type = GFX_VIDEO_TYPE_CS5530;
+#endif
+
+				/* Currently always CS5530 GPIOs for I2C access. */
+
+#if GFX_I2C_DYNAMIC
+				gfx_i2c_type = GFX_I2C_TYPE_GPIO;
+#endif
+
+#if GFX_TV_DYNAMIC
+				gfx_tv_type = GFX_TV_TYPE_FS451;
+#endif
+			}
+		}
+		else if (dir0 == 0xB0)
+		{
+			/* CHECK FOR SC1200 */
+
+			if ((dir1 == 0x70) || (dir1 == 0x81))
+			{
+				version = GFX_CPU_SC1200 | 
+					((((unsigned long) dir1 >> 4) )  << 8) | /* major */
+					((((unsigned long) dir1 & 0x0F)) << 16); /* minor */
+
+				/* Detect SC1200 revision */
+				
+				gfx_detect_chip();
+
+				/* SC1200 for video overlay and VIP. */
+
+#if GFX_VIDEO_DYNAMIC  
+				gfx_video_type = GFX_VIDEO_TYPE_SC1200;
+#endif		
+
+#if GFX_VIP_DYNAMIC
+				gfx_vip_type = GFX_VIP_TYPE_SC1200;
+#endif
+
+				/* Currently always SAA7114 decoder. */
+
+#if GFX_DECODER_DYNAMIC
+				gfx_decoder_type = GFX_DECODER_TYPE_SAA7114;
+#endif
+
+				/* SC1200 for TV encoder */
+
+#if GFX_TV_DYNAMIC
+				gfx_tv_type = GFX_TV_TYPE_SC1200; 
+#endif
+
+				/* Currently always ACCESS.bus for I2C access. */
+
+#if GFX_I2C_DYNAMIC
+				gfx_i2c_type = GFX_I2C_TYPE_ACCESS;
+#endif
+			}
+		}
+
+		if (version )
+		{
+			/* ALWAYS FIRST GENERATION GRAPHICS UNIT */
+
+#if GFX_DISPLAY_DYNAMIC
+			gfx_display_type = GFX_DISPLAY_TYPE_GU1;
+#endif
+#if GFX_2DACCEL_DYNAMIC
+			gfx_2daccel_type = GFX_2DACCEL_TYPE_GU1;
+#endif
+#if GFX_INIT_DYNAMIC
+			gfx_init_type = GFX_INIT_TYPE_GU1;
+#endif
+
+			/* READ THE CORE FREQUENCY  */
+
+			gfx_cpu_frequency = gfx_get_core_freq();
+		}
+	}
+
+#endif
+
+#if GFX_INIT_GU2
+	
+	value = gfx_pci_config_read(0x80000800);
+
+	if (value == PCI_VENDOR_DEVICE_REDCLOUD)
+	{
+		Q_WORD msr_value;
+		int valid, i;
+		
+		/* CHECK FOR SOFT VG */
+		/* If SoftVG is not present, the base addresses for all devices */
+		/* will not be allocated.  Essentially, it is as if no Redcloud */
+		/* video hardware is present.                                   */
+
+		value = gfx_pci_config_read (0x80000900);
+
+		if (value == REDCLOUD_VIDEO_PCI_VENDOR_DEVICE)
+		{
+			valid = 1;
+
+			/* BAR0 - BAR3 HOLD THE PERIPHERAL BASE ADDRESSES */
+
+			for (i = 0; i < 4; i++)
+			{
+				value = gfx_pci_config_read (0x80000910 + (i << 2));
+				if (value == 0x00000000 || value == 0xFFFFFFFF)
+				{
+					valid = 0;
+					break;
+				}
+			}
+
+			if (valid)
+			{
+				/* REDCLOUD INTEGRATED VIDEO             */
+
+#if GFX_VIDEO_DYNAMIC  
+				gfx_video_type = GFX_VIDEO_TYPE_REDCLOUD;
+#endif
+				
+				/* CURRENTLY, ALWAYS GPIO FOR I2C ACCESS */
+
+#if GFX_I2C_DYNAMIC
+				gfx_i2c_type = GFX_I2C_TYPE_GPIO;
+#endif
+
+				/* SECOND-GENERATION DISPLAY CONTROLLER  */
+
+#if GFX_DISPLAY_DYNAMIC
+				gfx_display_type = GFX_DISPLAY_TYPE_GU2;
+#endif
+
+				/* SECOND-GENERATION GRAPHICS UNIT       */
+
+#if GFX_2DACCEL_DYNAMIC
+				gfx_2daccel_type = GFX_2DACCEL_TYPE_GU2;
+#endif
+				
+				/* SECOND-GENERATION INITIALIZATION      */
+
+#if GFX_INIT_DYNAMIC
+				gfx_init_type = GFX_INIT_TYPE_GU2;
+#endif
+
+				/* MBUS MSR ACCESSES                     */
+
+#if GFX_MSR_DYNAMIC
+				gfx_msr_type = GFX_MSR_TYPE_REDCLOUD;
+#endif
+
+				/* CS5530 GPIO I2C */
+
+#if GFX_I2C_DYNAMIC
+				gfx_i2c_type = GFX_I2C_TYPE_GPIO;
+#endif
+
+				/* READ VERSION */
+
+				gfx_msr_init();
+
+				gfx_msr_read (RC_ID_MCP, MCP_RC_REVID, &msr_value);
+
+				/* SUBTRACT 1 FROM REV ID                                */
+				/* REDCLOUD 1.X rev id is 1 less than the reported value */
+
+				if ((msr_value.low & 0xF0) == 0x10)
+					msr_value.low--;
+
+				version = GFX_CPU_REDCLOUD        |
+					((msr_value.low & 0xF0) << 4) |    /* MAJOR */
+					((msr_value.low & 0x0F) << 16);    /* MINOR */
+
+				/* READ THE CORE FREQUENCY  */
+
+				gfx_cpu_frequency = gfx_get_core_freq();
+
+				/* SET THE GP SCRATCH AREA */
+				/* Color bitmap BLTs use the last 16K of frame buffer space */
+
+				gfx_gx2_scratch_base = gfx_get_frame_buffer_size() - 0x4000;
+			}	
+		}
+	}
+
+#endif
+
+	if (!version)
+	{
+		/* ALWAYS SECOND GENERATION IF SIMULATING */
+		/* For now, that is.  This could change.  */
+
+#if GFX_DISPLAY_DYNAMIC
+		gfx_display_type = GFX_DISPLAY_TYPE_GU2;
+#endif
+#if GFX_2DACCEL_DYNAMIC
+		gfx_2daccel_type = GFX_2DACCEL_TYPE_GU2;
+#endif
+#if GFX_INIT_DYNAMIC
+		gfx_init_type = GFX_INIT_TYPE_GU2;
+#endif
+#if GFX_MSR_DYNAMIC
+		gfx_msr_type = GFX_MSR_TYPE_REDCLOUD;
+#endif
+#if GFX_VIDEO_DYNAMIC
+		gfx_video_type = GFX_VIDEO_TYPE_REDCLOUD;
+#endif
+#if GFX_I2C_DYNAMIC
+		gfx_i2c_type = GFX_I2C_TYPE_GPIO;
+#endif
+	}
+	gfx_cpu_version = version;
+	
+	return(version);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_detect_video
+ * 
+ * This routine returns the type of the video hardware.
+ *
+ * The return value is as follows:
+ *     bits[7:0] = type (1 = CS5530, 2 = SC1200, 3 = Redcloud)
+ *
+ * Currently this routine does not actually detect any hardware, and bases
+ * the video hardware entirely on the detected CPU.
+ *-----------------------------------------------------------------------------
+ */
+unsigned long gfx_detect_video(void)
+{
+	unsigned long version = 0;
+	if ((gfx_cpu_version & 0xFF) == GFX_CPU_GXLV)
+		version = GFX_VID_CS5530;
+	else if ((gfx_cpu_version & 0xFF) == GFX_CPU_SC1200)
+		version = GFX_VID_SC1200;
+	else if ((gfx_cpu_version & 0xFF) == GFX_CPU_REDCLOUD)
+		version = GFX_VID_REDCLOUD;
+	gfx_vid_version = version;
+	return(version);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_pci_config_read
+ * 
+ * This routine reads a 32-bit value from the specified location in PCI
+ * configuration space.
+ *-----------------------------------------------------------------------------
+ */
+unsigned long gfx_pci_config_read(unsigned long address)
+{
+	unsigned long value = 0xFFFFFFFF;
+	OUTD(PCI_CONFIG_ADDR, address);
+	value = IND(PCI_CONFIG_DATA);
+	return(value);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_pci_config_write
+ * 
+ * This routine writes a 32-bit value to the specified location in PCI
+ * configuration space.
+ *-----------------------------------------------------------------------------
+ */
+void gfx_pci_config_write(unsigned long address, unsigned long data)
+{
+	OUTD(PCI_CONFIG_ADDR, address);
+	OUTD(PCI_CONFIG_DATA, data);
+	return;
+}
+
+/* WRAPPERS IF DYNAMIC SELECTION */
+/* Extra layer to call either first or second generation routines. */
+
+#if GFX_INIT_DYNAMIC
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_core_freq
+ *-----------------------------------------------------------------------------
+ */
+unsigned long gfx_get_core_freq(void)
+{
+	unsigned long freq = 0;
+#if GFX_INIT_GU1
+	if (gfx_init_type & GFX_INIT_TYPE_GU1)
+		freq = gu1_get_core_freq();
+#endif
+#if GFX_INIT_GU2
+	if (gfx_init_type & GFX_INIT_TYPE_GU2)
+		freq = gu2_get_core_freq();
+#endif
+	return freq;
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_cpu_register_base
+ *-----------------------------------------------------------------------------
+ */
+unsigned long gfx_get_cpu_register_base(void)
+{
+	unsigned long base = 0;
+	
+#if GFX_INIT_GU1	
+	if (gfx_init_type & GFX_INIT_TYPE_GU1)
+		base = gu1_get_cpu_register_base ();
+#endif
+#if GFX_INIT_GU2	
+	if (gfx_init_type & GFX_INIT_TYPE_GU2)
+		base = gu2_get_cpu_register_base ();
+#endif
+
+	return(base);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_graphics_register_base
+ *-----------------------------------------------------------------------------
+ */
+unsigned long gfx_get_graphics_register_base(void)
+{
+	unsigned long base = 0;
+	
+#if GFX_INIT_GU2
+	if (gfx_init_type & GFX_INIT_TYPE_GU2)
+		base = gu2_get_graphics_register_base ();
+#endif
+
+	return(base);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_frame_buffer_base
+ *-----------------------------------------------------------------------------
+ */
+unsigned long gfx_get_frame_buffer_base(void)
+{
+	unsigned long base = 0;
+	
+#if GFX_INIT_GU1	
+	if (gfx_init_type & GFX_INIT_TYPE_GU1)
+		base = gu1_get_frame_buffer_base ();
+#endif
+#if GFX_INIT_GU2	
+	if (gfx_init_type & GFX_INIT_TYPE_GU2)
+		base = gu2_get_frame_buffer_base ();
+#endif
+
+	return(base);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_frame_buffer_size
+ *-----------------------------------------------------------------------------
+ */
+unsigned long gfx_get_frame_buffer_size(void)
+{
+	unsigned long size = 0;
+
+#if GFX_INIT_GU1	
+	if (gfx_init_type & GFX_INIT_TYPE_GU1)
+		size = gu1_get_frame_buffer_size();
+#endif
+#if GFX_INIT_GU2	
+	if (gfx_init_type & GFX_INIT_TYPE_GU2)
+		size = gu2_get_frame_buffer_size();
+#endif
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_vid_register_base
+ *-----------------------------------------------------------------------------
+ */
+unsigned long gfx_get_vid_register_base(void)
+{
+	unsigned long base = 0;
+	
+#if GFX_INIT_GU1	
+	if (gfx_init_type & GFX_INIT_TYPE_GU1)
+		base = gu1_get_vid_register_base ();
+#endif
+#if GFX_INIT_GU2
+	if (gfx_init_type & GFX_INIT_TYPE_GU2)
+		base = gu2_get_vid_register_base ();
+#endif
+
+	return(base);
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_vip_register_base
+ *-----------------------------------------------------------------------------
+ */
+unsigned long gfx_get_vip_register_base(void)
+{
+	unsigned long base = 0;
+	
+#if GFX_INIT_GU1	
+	if (gfx_init_type & GFX_INIT_TYPE_GU1)
+		base = gu1_get_vip_register_base ();
+#endif
+
+	return(base);
+}
+
+#endif
+
+/* END OF FILE */
+
+
diff -uNr linux-2.4.31/drivers/video/nsc/gfx/gfx_mode.h linux-fb/drivers/video/nsc/gfx/gfx_mode.h
--- linux-2.4.31/drivers/video/nsc/gfx/gfx_mode.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/gfx/gfx_mode.h	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,124 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * This header file contains the mode tables.  It is used by the "gfx_disp.c" 
+ * file to set a display mode.
+ * </DOC_AMD_STD>
+ */
+
+#ifndef _gfx_mode_h
+#define _gfx_mode_h
+
+/* MODE FLAGS (BITWISE-OR) */
+
+#define GFX_MODE_8BPP		  0x00000001
+#define GFX_MODE_12BPP        0x00000002
+#define GFX_MODE_15BPP        0x00000004
+#define GFX_MODE_16BPP		  0x00000008
+#define GFX_MODE_24BPP        0x00000010
+#define GFX_MODE_56HZ         0x00000020
+#define GFX_MODE_60HZ		  0x00000040
+#define GFX_MODE_70HZ		  0x00000080
+#define GFX_MODE_72HZ		  0x00000100
+#define GFX_MODE_75HZ		  0x00000200
+#define GFX_MODE_85HZ		  0x00000400
+#define GFX_MODE_NEG_HSYNC	  0x00000800
+#define GFX_MODE_NEG_VSYNC	  0x00001000
+#define GFX_MODE_PIXEL_DOUBLE 0x00002000
+#define GFX_MODE_LINE_DOUBLE  0x00004000
+#define GFX_MODE_TV_NTSC      0x00008000
+#define GFX_MODE_TV_PAL       0x00010000
+
+#define GFX_MODE_LOCK_TIMING  0x10000000
+
+
+/* STRUCTURE DEFINITION */
+
+typedef struct tagDISPLAYMODE
+{
+	/* DISPLAY MODE FLAGS */
+	/* Specify valid color depths and the refresh rate. */
+
+	unsigned long flags;
+
+	/* TIMINGS */
+
+	unsigned short hactive; 
+	unsigned short hblankstart; 
+	unsigned short hsyncstart; 
+	unsigned short hsyncend; 
+	unsigned short hblankend; 
+	unsigned short htotal; 
+
+	unsigned short vactive;
+	unsigned short vblankstart;
+	unsigned short vsyncstart;
+	unsigned short vsyncend;
+	unsigned short vblankend;
+	unsigned short vtotal;
+
+	/* CLOCK FREQUENCY */
+	
+	unsigned long frequency;
+
+} DISPLAYMODE;
+
+
+/* For Fixed timings */
+typedef struct tagFIXEDTIMINGS
+{
+	/* DISPLAY MODE FLAGS */
+	/* Specify valid color depths and the refresh rate. */
+
+	int panelresx;
+	int panelresy;
+	unsigned short xres;
+	unsigned short yres;
+	
+	/* TIMINGS */
+
+	unsigned short hactive; 
+	unsigned short hblankstart; 
+	unsigned short hsyncstart; 
+	unsigned short hsyncend; 
+	unsigned short hblankend; 
+	unsigned short htotal; 
+
+	unsigned short vactive;
+	unsigned short vblankstart;
+	unsigned short vsyncstart;
+	unsigned short vsyncend;
+	unsigned short vblankend;
+	unsigned short vtotal;
+
+	/* CLOCK FREQUENCY */
+	
+	unsigned long frequency;
+
+} FIXEDTIMINGS;
+
+#endif /* !_gfx_mode_h */
+
+/* END OF FILE */
+
diff -uNr linux-2.4.31/drivers/video/nsc/gfx/gfx_msr.c linux-fb/drivers/video/nsc/gfx/gfx_msr.c
--- linux-2.4.31/drivers/video/nsc/gfx/gfx_msr.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/gfx/gfx_msr.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,135 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * This file contains routines to read machine-specific registers (MSRs)
+ * </DOC_AMD_STD>
+ */
+
+/* INCLUDE SUPPORT FOR REDCLOUD, IF SPECIFIED */
+
+#if GFX_MSR_REDCLOUD
+#include "msr_rdcl.c"
+#endif
+
+/* EXTRA WRAPPERS FOR DYNAMIC SELECTION */
+
+#if GFX_MSR_DYNAMIC
+
+/*-----------------------------------------------------------------------------
+ * gfx_msr_init
+ *-----------------------------------------------------------------------------
+ */
+int gfx_msr_init ()
+{
+	int ret_value = 0;
+
+#if GFX_MSR_REDCLOUD
+	if (gfx_msr_type & GFX_MSR_TYPE_REDCLOUD)
+		ret_value = redcloud_msr_init();
+#endif
+
+	return ret_value;
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_id_msr_device
+ *-----------------------------------------------------------------------------
+ */
+DEV_STATUS gfx_id_msr_device (MSR *pDev, unsigned long address)
+{
+	DEV_STATUS ret_value = NOT_KNOWN;
+
+#if GFX_MSR_REDCLOUD
+	if (gfx_msr_type & GFX_MSR_TYPE_REDCLOUD)
+		ret_value = redcloud_id_msr_device(pDev, address);
+#endif
+
+	return ret_value;
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_msr_dev_address
+ *-----------------------------------------------------------------------------
+ */
+DEV_STATUS gfx_get_msr_dev_address (unsigned int device, unsigned long *address)
+{
+	DEV_STATUS ret_value = NOT_KNOWN;
+
+#if GFX_MSR_REDCLOUD
+	if (gfx_msr_type & GFX_MSR_TYPE_REDCLOUD)
+		ret_value = redcloud_get_msr_dev_address (device, address);
+#endif
+
+	return ret_value;
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_get_glink_id_at_address
+ *-----------------------------------------------------------------------------
+ */
+DEV_STATUS gfx_get_glink_id_at_address(unsigned int *device, unsigned long address)
+{
+	DEV_STATUS ret_value = NOT_KNOWN;
+
+#if GFX_MSR_REDCLOUD
+	if (gfx_msr_type & GFX_MSR_TYPE_REDCLOUD)
+		ret_value = redcloud_get_glink_id_at_address (device, address);
+#endif
+
+	return ret_value;
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_msr_read
+ *-----------------------------------------------------------------------------
+ */
+DEV_STATUS gfx_msr_read (unsigned int device, unsigned int msrRegister, Q_WORD *msrValue)
+{
+	DEV_STATUS ret_value = NOT_KNOWN;
+
+#if GFX_MSR_REDCLOUD
+	if (gfx_msr_type & GFX_MSR_TYPE_REDCLOUD)
+		ret_value = redcloud_msr_read (device, msrRegister, msrValue);
+#endif
+
+	return ret_value;
+}
+
+/*-----------------------------------------------------------------------------
+ * gfx_msr_write
+ *-----------------------------------------------------------------------------
+ */
+DEV_STATUS gfx_msr_write (unsigned int device, unsigned int msrRegister, Q_WORD *msrValue)
+{
+	DEV_STATUS ret_value = NOT_KNOWN;
+
+#if GFX_MSR_REDCLOUD
+	if (gfx_msr_type & GFX_MSR_TYPE_REDCLOUD)
+		ret_value = redcloud_msr_write(device, msrRegister, msrValue);
+#endif
+
+	return ret_value;
+}
+
+#endif
diff -uNr linux-2.4.31/drivers/video/nsc/gfx/gfx_priv.h linux-fb/drivers/video/nsc/gfx/gfx_priv.h
--- linux-2.4.31/drivers/video/nsc/gfx/gfx_priv.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/gfx/gfx_priv.h	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,929 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * This header file contains the prototypes for local and private routines.
+ * </DOC_AMD_STD>
+ */
+
+/*---------------------------------*/
+/* FIRST GENERATION INITIALIZATION */
+/*---------------------------------*/
+
+#if GFX_INIT_GU1
+
+/* PRIVATE ROUTINES */
+
+unsigned char gfx_gxm_config_read(unsigned char index);
+
+/* DYNAMIC ROUTINES */
+
+#if GFX_INIT_DYNAMIC
+unsigned long gu1_get_core_freq(void);
+unsigned long gu1_get_cpu_register_base(void);
+unsigned long gu1_get_graphics_register_base(void);
+unsigned long gu1_get_frame_buffer_base(void);
+unsigned long gu1_get_frame_buffer_size(void);
+unsigned long gu1_get_vid_register_base(void);
+unsigned long gu1_get_vip_register_base(void);
+#endif
+
+#endif
+
+/*----------------------------------*/
+/* SECOND GENERATION INITIALIZATION */
+/*----------------------------------*/
+
+#if GFX_INIT_GU2
+
+/* DYNAMIC ROUTINES */
+
+#if GFX_INIT_DYNAMIC
+unsigned long gu2_get_core_freq(void);
+unsigned long gu2_get_cpu_register_base(void);
+unsigned long gu2_get_graphics_register_base(void);
+unsigned long gu2_get_frame_buffer_base(void);
+unsigned long gu2_get_frame_buffer_size(void);
+unsigned long gu2_get_vid_register_base(void);
+unsigned long gu2_get_vip_register_base(void);
+#endif
+
+#endif
+
+/*----------------------------------*/
+/* MSR ROUTINES                     */
+/*----------------------------------*/
+
+#if GFX_MSR_REDCLOUD
+
+/* PRIVATE ROUTINES */
+
+void redcloud_build_mbus_tree(void);
+int redcloud_init_msr_devices(MSR aDev[], unsigned int array_size);
+DEV_STATUS redcloud_find_msr_device (MSR *pDev);
+
+/* DYNAMIC ROUTINES */
+
+#if GFX_MSR_DYNAMIC
+int redcloud_msr_init (void);
+DEV_STATUS redcloud_id_msr_device (MSR *pDev, unsigned long address);
+DEV_STATUS redcloud_get_msr_dev_address (unsigned int device, unsigned long *address);
+DEV_STATUS redcloud_get_glink_id_at_address(unsigned int *device, unsigned long address);
+DEV_STATUS redcloud_msr_read (unsigned int device, unsigned int msrRegister, Q_WORD *msrValue);
+DEV_STATUS redcloud_msr_write (unsigned int device, unsigned int msrRegister, Q_WORD *msrValue);
+#endif
+
+#endif
+
+void gfx_set_display_video_enable(int enable);
+void gfx_set_display_video_size(unsigned short width, unsigned short height);
+void gfx_set_display_video_offset(unsigned long offset);
+unsigned long gfx_get_display_video_offset(void);
+unsigned long gfx_get_display_video_size(void);
+
+/*----------------------------------*/
+/* FIRST GENERATION DISPLAY         */
+/*----------------------------------*/
+
+#if GFX_DISPLAY_GU1
+
+/* PRIVATE ROUTINES */
+
+void gu1_enable_compression(void);
+void gu1_disable_compression(void);
+void gu1_delay_approximate (unsigned long milliseconds);
+void gu1_delay_precise (unsigned long milliseconds);
+
+/* DYNAMIC ROUTINES */
+
+#if GFX_DISPLAY_DYNAMIC
+void gu1_set_display_video_enable(int enable);
+void gu1_set_display_video_size(unsigned short width, unsigned short height);
+void gu1_set_display_video_offset(unsigned long offset);
+unsigned long gu1_get_display_video_offset(void);
+unsigned long gu1_get_display_video_size(void);
+int gu1_set_display_bpp (unsigned short bpp);
+int gu1_is_display_mode_supported(int xres, int yres, int bpp, int hz);
+int gu1_set_display_mode(int xres, int yres, int bpp, int hz);
+int	gu1_set_display_timings(unsigned short bpp, unsigned short flags,
+	unsigned short hactive, unsigned short hblank_start, 
+	unsigned short hsync_start, unsigned short hsync_end, 
+	unsigned short hblank_end, unsigned short htotal, 
+    unsigned short vactive, unsigned short vblank_start, 
+	unsigned short vsync_start, unsigned short vsync_end, 
+	unsigned short vblank_end, unsigned short vtotal,
+	unsigned long frequency);
+int gu1_set_vtotal(unsigned short vtotal);	
+void gu1_set_display_pitch(unsigned short pitch);
+void gu1_set_display_offset(unsigned long offset);
+int gu1_set_display_palette_entry(unsigned long index, unsigned long palette);
+int gu1_set_display_palette(unsigned long *palette);
+void gu1_video_shutdown(void);
+void gu1_set_cursor_enable(int enable);
+void gu1_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor);
+void gu1_set_cursor_position(unsigned long memoffset, 
+	unsigned short xpos, unsigned short ypos, 
+	unsigned short xhotspot, unsigned short yhotspot);
+void gu1_set_cursor_shape32(unsigned long memoffset, 
+	unsigned long *andmask, unsigned long *xormask);
+int gu1_set_compression_enable(int enable);
+int gu1_set_compression_offset(unsigned long offset);
+int gu1_set_compression_pitch(unsigned short pitch);
+int gu1_set_compression_size(unsigned short size);
+void gu1_set_display_priority_high(int enable);
+int gu1_test_timing_active(void);
+int gu1_test_vertical_active(void);
+int gu1_wait_vertical_blank(void);
+void gu1_delay_milliseconds(unsigned long milliseconds);
+void gu1_delay_microseconds(unsigned long microseconds);
+void gu1_enable_panning(int x, int y);
+int gu1_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp);
+int gu1_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp);
+void gu1_reset_timing_lock(void);
+int gu1_get_display_details(unsigned int mode, int *xres, int *yres, int *hz);
+unsigned short gu1_get_display_pitch(void);
+unsigned long gu1_get_max_supported_pixel_clock (void);
+int gu1_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency);
+int gu1_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency);
+int gu1_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency);
+int gu1_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency);
+int gu1_get_display_mode_count(void);
+int gu1_get_display_mode(int *xres, int *yres, int *bpp, int *hz);
+unsigned long gu1_get_frame_buffer_line_size (void);
+unsigned short gu1_get_hactive(void);
+unsigned short gu1_get_hblank_start(void);
+unsigned short gu1_get_hsync_start(void);
+unsigned short gu1_get_hsync_end(void);
+unsigned short gu1_get_hblank_end(void);
+unsigned short gu1_get_htotal(void);
+unsigned short gu1_get_vactive(void);
+unsigned short gu1_get_vline(void);
+unsigned short gu1_get_vblank_start(void);
+unsigned short gu1_get_vsync_start(void);
+unsigned short gu1_get_vsync_end(void);
+unsigned short gu1_get_vblank_end(void);
+unsigned short gu1_get_vtotal(void);
+unsigned short gu1_get_display_bpp(void);
+unsigned long gu1_get_display_offset(void);
+int gu1_get_display_palette_entry(unsigned long index, unsigned long *palette);
+void gu1_get_display_palette(unsigned long *palette);
+unsigned long gu1_get_cursor_enable(void);
+unsigned long gu1_get_cursor_offset(void);
+unsigned long gu1_get_cursor_position(void);
+unsigned long gu1_get_cursor_clip(void);
+unsigned long gu1_get_cursor_color(int color);
+unsigned long gu1_get_icon_enable(void);
+unsigned long gu1_get_icon_offset (void);
+unsigned long gu1_get_icon_position (void);
+unsigned long gu1_get_icon_color (int color);
+int gu1_get_compression_enable(void);
+unsigned long gu1_get_compression_offset(void);
+unsigned short gu1_get_compression_pitch(void);
+unsigned short gu1_get_compression_size(void);
+int gu1_get_display_priority_high(void);
+int gu1_get_valid_bit(int line);
+#endif
+
+#endif
+
+void gfx_set_display_video_format(unsigned long format);
+void gfx_set_display_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, 
+									   unsigned long voffset);
+void gfx_set_display_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch);
+void gfx_set_display_video_downscale (unsigned short srch, unsigned short dsth);
+void gfx_set_display_video_vertical_downscale_enable(int enable);
+void gfx_get_display_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, 
+									   unsigned long *voffset);
+void gfx_get_display_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch);
+unsigned long gfx_get_display_video_downscale_delta(void);
+int gfx_get_display_video_downscale_enable(void); 
+
+/*----------------------------------*/
+/* SECOND GENERATION DISPLAY        */
+/*----------------------------------*/
+
+#if GFX_DISPLAY_GU2
+
+/* PRIVATE ROUTINES */
+
+void gu2_enable_compression(void);
+void gu2_disable_compression(void);
+
+/* DYNAMIC ROUTINES */
+
+#if GFX_DISPLAY_DYNAMIC
+void gu2_get_display_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, 
+									   unsigned long *voffset);
+void gu2_get_display_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch);
+unsigned long gu2_get_display_video_downscale_delta(void);
+int gu2_get_display_video_downscale_enable(void);
+void gu2_set_display_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, 
+									   unsigned long voffset);
+void gu2_set_display_video_format(unsigned long format);
+void gu2_set_display_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch);
+void gu2_set_display_video_downscale (unsigned short srch, unsigned short dsth);
+void gu2_set_display_video_vertical_downscale_enable(int enable);
+void gu2_set_display_video_enable(int enable);
+void gu2_set_display_video_size(unsigned short width, unsigned short height);
+void gu2_set_display_video_offset(unsigned long offset);
+unsigned long gu2_get_display_video_offset(void);
+unsigned long gu2_get_display_video_size(void);
+int gu2_set_display_bpp (unsigned short bpp);
+int gu2_is_display_mode_supported(int xres, int yres, int bpp, int hz);
+int gu2_set_display_mode(int xres, int yres, int bpp, int hz);
+int	gu2_set_display_timings(unsigned short bpp, unsigned short flags,
+	unsigned short hactive, unsigned short hblank_start, 
+	unsigned short hsync_start, unsigned short hsync_end, 
+	unsigned short hblank_end, unsigned short htotal, 
+    unsigned short vactive, unsigned short vblank_start, 
+	unsigned short vsync_start, unsigned short vsync_end, 
+	unsigned short vblank_end, unsigned short vtotal,
+	unsigned long frequency);
+int gu2_set_vtotal(unsigned short vtotal);	
+void gu2_set_display_pitch(unsigned short pitch);
+void gu2_set_display_offset(unsigned long offset);
+int gu2_set_display_palette_entry(unsigned long index, unsigned long palette);
+int gu2_set_display_palette(unsigned long *palette);
+void gu2_set_cursor_enable(int enable);
+void gu2_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor);
+void gu2_set_cursor_position(unsigned long memoffset, 
+	unsigned short xpos, unsigned short ypos, 
+	unsigned short xhotspot, unsigned short yhotspot);
+void gu2_set_cursor_shape32(unsigned long memoffset, 
+	unsigned long *andmask, unsigned long *xormask);
+void gu2_set_cursor_shape64(unsigned long memoffset, 
+	unsigned long *andmask, unsigned long *xormask);
+void gu2_set_icon_enable (int enable);
+void gu2_set_icon_colors (unsigned long color0, unsigned long color1, unsigned long color2);
+void gu2_set_icon_position (unsigned long memoffset, unsigned short xpos);
+void gu2_set_icon_shape64 (unsigned long memoffset, unsigned long *andmask, 
+						   unsigned long *xormask, unsigned int lines);
+int gu2_set_compression_enable(int enable);
+int gu2_set_compression_offset(unsigned long offset);
+int gu2_set_compression_pitch(unsigned short pitch);
+int gu2_set_compression_size(unsigned short size);
+void gu2_set_display_priority_high(int enable);
+int gu2_test_timing_active(void);
+int gu2_test_vertical_active(void);
+int gu2_wait_vertical_blank(void);
+void gu2_delay_milliseconds(unsigned long milliseconds);
+void gu2_delay_microseconds(unsigned long microseconds);
+void gu2_enable_panning(int x, int y);
+int gu2_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp);
+int gu2_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp);
+void gu2_reset_timing_lock(void);
+int gu2_get_display_details(unsigned int mode, int *xres, int *yres, int *hz);
+unsigned short gu2_get_display_pitch(void);
+unsigned long gu2_get_max_supported_pixel_clock (void);
+int gu2_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency);
+int gu2_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency);
+int gu2_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency);
+int gu2_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency);
+int gu2_get_display_mode_count(void);
+int gu2_get_display_mode(int *xres, int *yres, int *bpp, int *hz);
+unsigned long gu2_get_frame_buffer_line_size (void);
+unsigned short gu2_get_hactive(void);
+unsigned short gu2_get_hblank_start(void);
+unsigned short gu2_get_hsync_start(void);
+unsigned short gu2_get_hsync_end(void);
+unsigned short gu2_get_hblank_end(void);
+unsigned short gu2_get_htotal(void);
+unsigned short gu2_get_vactive(void);
+unsigned short gu2_get_vline(void);
+unsigned short gu2_get_vblank_start(void);
+unsigned short gu2_get_vsync_start(void);
+unsigned short gu2_get_vsync_end(void);
+unsigned short gu2_get_vblank_end(void);
+unsigned short gu2_get_vtotal(void);
+unsigned short gu2_get_display_bpp(void);
+unsigned long gu2_get_display_offset(void);
+int gu2_get_display_palette_entry(unsigned long index, unsigned long *palette);
+void gu2_get_display_palette(unsigned long *palette);
+unsigned long gu2_get_cursor_enable(void);
+unsigned long gu2_get_cursor_offset(void);
+unsigned long gu2_get_cursor_position(void);
+unsigned long gu2_get_cursor_clip(void);
+unsigned long gu2_get_cursor_color(int color);
+unsigned long gu2_get_icon_enable(void);
+unsigned long gu2_get_icon_offset (void);
+unsigned long gu2_get_icon_position (void);
+unsigned long gu2_get_icon_color (int color);
+int gu2_get_compression_enable(void);
+unsigned long gu2_get_compression_offset(void);
+unsigned short gu2_get_compression_pitch(void);
+unsigned short gu2_get_compression_size(void);
+int gu2_get_valid_bit(int line);
+#endif
+
+#endif
+
+/*----------------------------------*/
+/* FIRST GENERATION 2D ACCELERATION */
+/*----------------------------------*/
+
+#if GFX_2DACCEL_GU1
+
+/* PRIVATE ROUTINES */
+
+void gu1_solid_fill(unsigned short x, unsigned short y, 
+	unsigned short width, unsigned short height, unsigned long color);
+void gu1_detect_blt_buffer_base(void);
+
+/* DYNAMIC ROUTINES */
+
+#if GFX_2DACCEL_DYNAMIC
+void gu1_set_bpp(unsigned short bpp);
+void gu1_set_solid_pattern(unsigned long color);
+void gu1_set_mono_pattern(unsigned long bgcolor, unsigned long fgcolor, 
+	unsigned long data0, unsigned long data1, unsigned char transparency);
+void gu1_set_color_pattern(unsigned long bgcolor, unsigned long fgcolor, 
+	unsigned long data0, unsigned long data1,unsigned long data2,unsigned long data3, unsigned char transparency);
+void gu1_load_color_pattern_line (short y, unsigned long *pattern_8x8);
+void gu1_set_solid_source(unsigned long color);
+void gu1_set_mono_source(unsigned long bgcolor, unsigned long fgcolor,
+	unsigned short transparent);
+void gu1_set_pattern_flags(unsigned short flags);
+void gu1_set_raster_operation(unsigned char rop);
+void gu1_pattern_fill(unsigned short x, unsigned short y, 
+	unsigned short width, unsigned short height);
+void gu1_color_pattern_fill(unsigned short x, unsigned short y, 
+	unsigned short width, unsigned short height, unsigned long *pattern);
+void gu1_screen_to_screen_blt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height);
+void gu1_screen_to_screen_xblt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned long color);
+void gu1_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned char *data, long pitch); 
+void gu1_color_bitmap_to_screen_xblt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned char *data, long pitch, 
+	unsigned long color); 
+void gu1_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned char *data, short pitch); 
+void gu1_text_blt(unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned char *data);
+void gu1_bresenham_line(unsigned short x, unsigned short y, 
+	unsigned short length, unsigned short initerr, 
+	unsigned short axialerr, unsigned short diagerr, 
+	unsigned short flags);
+void gu1_wait_until_idle(void);
+int gu1_test_blt_pending(void);
+#endif
+
+#endif
+
+/*-----------------------------------*/
+/* SECOND GENERATION 2D ACCELERATION */
+/*-----------------------------------*/
+
+#if GFX_2DACCEL_GU2
+
+/* DYNAMIC ROUTINES */
+
+#if GFX_2DACCEL_DYNAMIC
+void gfx_reset_pitch(unsigned short pitch);
+void gu2_reset_pitch(unsigned short pitch);
+void gu2_set_bpp(unsigned short bpp);
+void gu2_set_solid_pattern(unsigned long color);
+void gu2_set_mono_pattern(unsigned long bgcolor, unsigned long fgcolor, 
+	unsigned long data0, unsigned long data1, unsigned char transparency);
+void gu2_set_color_pattern(unsigned long bgcolor, unsigned long fgcolor, 
+	unsigned long data0, unsigned long data1,unsigned long data2,unsigned long data3, unsigned char transparency);
+void gu2_load_color_pattern_line (short y, unsigned long *pattern_8x8);
+void gu2_set_solid_source(unsigned long color);
+void gu2_set_mono_source(unsigned long bgcolor, unsigned long fgcolor,
+	unsigned short transparent);
+void gu2_set_pattern_flags(unsigned short flags);
+void gu2_set_raster_operation(unsigned char rop);
+void gu2_pattern_fill(unsigned short x, unsigned short y, 
+	unsigned short width, unsigned short height);
+void gu2_color_pattern_fill(unsigned short x, unsigned short y, 
+	unsigned short width, unsigned short height, unsigned long *pattern);
+void gu2_screen_to_screen_blt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height);
+void gu2_screen_to_screen_xblt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned long color);
+void gu2_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned char *data, long pitch); 
+void gu2_color_bitmap_to_screen_xblt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned char *data, long pitch, 
+	unsigned long color); 
+void gu2_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned char *data, short pitch); 
+void gu2_text_blt(unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned char *data);
+void gu2_bresenham_line(unsigned short x, unsigned short y, 
+	unsigned short length, unsigned short initerr, 
+	unsigned short axialerr, unsigned short diagerr, 
+	unsigned short flags);
+void gu2_wait_until_idle(void);
+int gu2_test_blt_pending(void);
+
+void gu22_set_source_stride(unsigned short stride);
+void gu22_set_destination_stride(unsigned short stride);
+void gu22_set_pattern_origin(int x, int y);
+void gu22_set_source_transparency(unsigned long color, unsigned long mask);
+void gu22_set_alpha_mode(int mode);
+void gu22_set_alpha_value(unsigned char value);
+void gu22_pattern_fill(unsigned long dstoffset, unsigned short width, 
+	unsigned short height);
+void gu22_color_pattern_fill(unsigned long dstoffset, unsigned short width, 
+	unsigned short height, unsigned long *pattern);
+void gu22_screen_to_screen_blt(unsigned long srcoffset, unsigned long dstoffset, 
+	unsigned short width, unsigned short height, int flags);
+void gu22_mono_expand_blt(unsigned long srcbase, unsigned short srcx, 
+	unsigned short srcy, unsigned long dstoffset, unsigned short width, 
+	unsigned short height, int byte_packed);
+void gu22_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy,
+	unsigned long dstoffset, unsigned short width, unsigned short height, 
+	unsigned char *data, short pitch);
+void gu22_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy,
+	unsigned long dstoffset, unsigned short width, unsigned short height, 
+	unsigned char *data, short pitch);
+void gu22_text_blt (unsigned long dstoffset, unsigned short width, unsigned short height, 
+					unsigned char *data);
+void gu22_bresenham_line(unsigned long dstoffset, 
+	unsigned short length, unsigned short initerr, 
+	unsigned short axialerr, unsigned short diagerr, 
+	unsigned short flags);
+void gu22_sync_to_vblank(void);
+#endif
+
+#endif
+
+void gfx_reset_video(void);
+int gfx_set_display_control(int sync_polarities);
+int gfx_set_screen_enable(int enable);
+
+/*-----------------------*/
+/* CS5530 VIDEO ROUTINES */
+/*-----------------------*/
+
+#if GFX_VIDEO_CS5530
+
+/* PRIVATE ROUTINES */
+
+/* DYNAMIC ROUTINES */
+
+#if GFX_VIDEO_DYNAMIC
+void cs5530_reset_video(void);
+int cs5530_set_display_control(int sync_polarities);
+void cs5530_set_clock_frequency(unsigned long frequency);
+unsigned long cs5530_get_clock_frequency(void);
+int cs5530_set_crt_enable(int enable);
+int cs5530_get_sync_polarities(void);
+int cs5530_get_vsa2_softvga_enable(void);
+int cs5530_set_video_enable(int enable);
+int cs5530_set_video_format(unsigned long format);
+int cs5530_set_video_size(unsigned short width, unsigned short height);
+int cs5530_set_video_offset(unsigned long offset);
+int cs5530_set_video_window(short x, short y, unsigned short w, unsigned short h);
+int cs5530_set_video_left_crop(unsigned short x);
+int cs5530_set_video_scale(unsigned short srcw, unsigned short srch, 
+	unsigned short dstw, unsigned short dsth);
+int cs5530_set_video_color_key(unsigned long key, unsigned long mask, 
+	int bluescreen);
+int cs5530_set_video_filter(int xfilter, int yfilter);
+int cs5530_set_video_palette(unsigned long *palette);
+int cs5530_set_video_palette_entry (unsigned long index, unsigned long color);
+int cs5530_disable_softvga(void);
+int cs5530_enable_softvga(void);
+
+/* READ ROUTINES IN GFX_VID.C */
+
+int cs5530_get_video_enable(void);
+int cs5530_get_video_format(void);
+unsigned long cs5530_get_video_src_size(void);
+unsigned long cs5530_get_video_line_size(void);
+unsigned long cs5530_get_video_xclip(void);
+unsigned long cs5530_get_video_offset(void);
+unsigned long cs5530_get_video_upscale(void);
+unsigned long cs5530_get_video_scale(void);  
+unsigned long cs5530_get_video_dst_size(void);
+unsigned long cs5530_get_video_position(void);
+unsigned long cs5530_get_video_color_key(void);
+unsigned long cs5530_get_video_color_key_mask(void);
+int cs5530_get_video_palette_entry(unsigned long index, unsigned long *palette);
+int cs5530_get_video_color_key_src(void);
+int cs5530_get_video_filter(void);
+unsigned long cs5530_read_crc(void);
+#endif
+#endif
+
+/*-----------------------*/
+/* SC1200 VIDEO ROUTINES */
+/*-----------------------*/
+
+#if GFX_VIDEO_SC1200
+
+/* PRIVATE ROUTINES */
+
+/* DYNAMIC ROUTINES */
+
+#if GFX_VIDEO_DYNAMIC
+void sc1200_reset_video(void);
+int sc1200_set_display_control(int sync_polarities);
+int sc1200_set_screen_enable(int enable);
+void sc1200_set_clock_frequency(unsigned long frequency);
+unsigned long sc1200_get_clock_frequency(void);
+int sc1200_set_crt_enable(int enable);
+int sc1200_get_sync_polarities(void);
+int sc1200_get_vsa2_softvga_enable(void);
+int sc1200_set_video_enable(int enable);
+int sc1200_set_video_format(unsigned long format);
+int sc1200_set_video_size(unsigned short width, unsigned short height);
+int sc1200_set_video_offset(unsigned long offset);
+int sc1200_set_video_window(short x, short y, unsigned short w, unsigned short h);
+int sc1200_set_video_left_crop(unsigned short x);
+int sc1200_set_video_upscale(unsigned short srcw, unsigned short srch, 
+	unsigned short dstw, unsigned short dsth);
+int sc1200_set_video_scale(unsigned short srcw, unsigned short srch, 
+	unsigned short dstw, unsigned short dsth);
+int sc1200_set_video_downscale_config(unsigned short type, unsigned short m);
+int sc1200_set_video_color_key(unsigned long key, unsigned long mask, 
+	int bluescreen);
+int sc1200_set_video_filter(int xfilter, int yfilter);
+int sc1200_set_video_palette(unsigned long *palette);
+int sc1200_set_video_palette_entry (unsigned long index, unsigned long color);
+int sc1200_set_video_downscale_coefficients(unsigned short coef1, unsigned short coef2,
+										 unsigned short coef3, unsigned short coef4) ;
+int sc1200_set_video_downscale_enable(int enable);										 
+int sc1200_set_video_source(VideoSourceType source);
+int sc1200_set_vbi_source(VbiSourceType source);
+int sc1200_set_vbi_lines(unsigned long even, unsigned long odd);
+int sc1200_set_vbi_total(unsigned long even, unsigned long odd);
+int sc1200_set_video_interlaced(int enable);
+int sc1200_set_color_space_YUV(int enable);
+int sc1200_set_vertical_scaler_offset(char offset);
+int sc1200_set_top_line_in_odd(int enable);
+int sc1200_set_genlock_delay(unsigned long delay);
+int sc1200_set_genlock_enable(int flags);
+int sc1200_set_video_cursor(unsigned long key, unsigned long mask, unsigned short select_color2,
+						 unsigned long color1, unsigned long color2);
+int sc1200_set_video_request(short x, short y);
+
+int sc1200_select_alpha_region(int region);
+int sc1200_set_alpha_enable(int enable);
+int sc1200_set_alpha_window(short x, short y, 
+	unsigned short width, unsigned short height);
+int sc1200_set_alpha_value(unsigned char alpha, char delta);
+int sc1200_set_alpha_priority(int priority);
+int sc1200_set_alpha_color(unsigned long color);
+int sc1200_set_alpha_color_enable(int enable);
+int sc1200_set_no_ck_outside_alpha(int enable);
+int sc1200_disable_softvga(void);
+int sc1200_enable_softvga(void);
+int sc1200_set_macrovision_enable(int enable);
+
+/* READ ROUTINES IN GFX_VID.C */
+
+int sc1200_get_video_enable(void);
+int sc1200_get_video_format(void);
+unsigned long sc1200_get_video_src_size(void);
+unsigned long sc1200_get_video_line_size(void);
+unsigned long sc1200_get_video_xclip(void);
+unsigned long sc1200_get_video_offset(void);
+unsigned long sc1200_get_video_upscale(void);
+unsigned long sc1200_get_video_scale(void);
+int sc1200_get_video_downscale_config(unsigned short *type, unsigned short *m);
+void sc1200_get_video_downscale_coefficients(unsigned short *coef1, unsigned short *coef2,
+										  unsigned short *coef3, unsigned short *coef4);
+void sc1200_get_video_downscale_enable(int *enable);									  
+unsigned long sc1200_get_video_dst_size(void);
+unsigned long sc1200_get_video_position(void);
+unsigned long sc1200_get_video_color_key(void);
+unsigned long sc1200_get_video_color_key_mask(void);
+int sc1200_get_video_palette_entry(unsigned long index, unsigned long *palette);
+int sc1200_get_video_color_key_src(void);
+int sc1200_get_video_filter(void);
+int sc1200_get_video_request(short *x, short *y);
+int sc1200_get_video_source(VideoSourceType *source);
+int sc1200_get_vbi_source(VbiSourceType *source);
+unsigned long sc1200_get_vbi_lines(int odd);
+unsigned long sc1200_get_vbi_total(int odd);
+int sc1200_get_video_interlaced(void);
+int sc1200_get_color_space_YUV(void);
+int sc1200_get_vertical_scaler_offset(char *offset);
+unsigned long sc1200_get_genlock_delay(void);
+int sc1200_get_genlock_enable(void);
+int sc1200_get_video_cursor(unsigned long *key, unsigned long *mask, unsigned short *select_color2,
+						 unsigned long *color1, unsigned short *color2);
+unsigned long sc1200_read_crc(void);
+int sc1200_get_macrovision_enable(void);
+
+void sc1200_get_alpha_enable(int *enable);
+void sc1200_get_alpha_size(unsigned short *x, unsigned short *y, 
+	unsigned short *width, unsigned short *height);
+void sc1200_get_alpha_value(unsigned char *alpha, char *delta);
+void sc1200_get_alpha_priority(int *priority);
+void sc1200_get_alpha_color(unsigned long *color);
+#endif
+#endif
+
+/*-------------------------*/
+/* REDCLOUD VIDEO ROUTINES */
+/*-------------------------*/
+
+#if GFX_VIDEO_REDCLOUD
+
+/* PRIVATE ROUTINES */
+
+/* DYNAMIC ROUTINES */
+
+#if GFX_VIDEO_DYNAMIC
+void redcloud_reset_video(void);
+int redcloud_set_display_control(int sync_polarities);
+void redcloud_set_clock_frequency(unsigned long frequency);
+unsigned long redcloud_get_clock_frequency(void);
+int redcloud_set_crt_enable(int enable);
+int redcloud_get_sync_polarities(void);
+int redcloud_set_video_enable(int enable);
+int redcloud_set_video_format(unsigned long format);
+int redcloud_set_video_size(unsigned short width, unsigned short height);
+int redcloud_set_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch);
+int redcloud_set_video_offset(unsigned long offset);
+int redcloud_set_video_yuv_offsets (unsigned long yoffset, unsigned long uoffset,
+							   unsigned long voffset);
+int redcloud_set_video_window(short x, short y, unsigned short w, unsigned short h);
+int redcloud_set_video_left_crop(unsigned short x);
+int redcloud_set_video_scale(unsigned short srcw, unsigned short srch, 
+	unsigned short dstw, unsigned short dsth);
+int redcloud_set_video_vertical_downscale(unsigned short srch, unsigned short dsth);
+void redcloud_set_video_vertical_downscale_enable (int enable);
+int redcloud_set_video_downscale_config(unsigned short type, unsigned short m);
+int redcloud_set_video_color_key(unsigned long key, unsigned long mask, 
+	int bluescreen);
+int redcloud_set_video_filter(int xfilter, int yfilter);
+int redcloud_set_video_palette(unsigned long *palette);
+int redcloud_set_video_palette_entry (unsigned long index, unsigned long color);
+int redcloud_set_video_downscale_coefficients(unsigned short coef1, unsigned short coef2,
+										 unsigned short coef3, unsigned short coef4) ;
+int redcloud_set_video_downscale_enable(int enable);										 
+int redcloud_set_video_cursor(unsigned long key, unsigned long mask, unsigned short select_color2,
+						 unsigned long color1, unsigned long color2);
+int redcloud_set_video_cursor_enable (int enable);
+
+int redcloud_select_alpha_region(int region);
+int redcloud_set_alpha_enable(int enable);
+int redcloud_set_alpha_window(short x, short y, 
+	unsigned short width, unsigned short height);
+int redcloud_set_alpha_value(unsigned char alpha, char delta);
+int redcloud_set_alpha_priority(int priority);
+int redcloud_set_alpha_color(unsigned long color);
+int redcloud_set_alpha_color_enable(int enable);
+int redcloud_set_no_ck_outside_alpha(int enable);
+int redcloud_set_video_request(short x, short y);
+
+/* READ ROUTINES IN GFX_VID.C */
+
+int redcloud_get_video_enable(void);
+int redcloud_get_video_format(void);
+unsigned long redcloud_get_video_src_size(void);
+unsigned long redcloud_get_video_line_size(void);
+unsigned long redcloud_get_video_xclip(void);
+unsigned long redcloud_get_video_offset(void);
+void redcloud_get_video_yuv_offsets (unsigned long *yoffset, unsigned long *uoffset, 
+								unsigned long *voffset);
+void redcloud_get_video_yuv_pitch (unsigned long *ypitch, unsigned long *uvpitch);
+unsigned long redcloud_get_video_scale(void);
+unsigned long redcloud_get_video_downscale_delta(void);
+int redcloud_get_video_vertical_downscale_enable (void);
+int redcloud_get_video_downscale_config(unsigned short *type, unsigned short *m);
+void redcloud_get_video_downscale_coefficients(unsigned short *coef1, unsigned short *coef2,
+										  unsigned short *coef3, unsigned short *coef4);
+void redcloud_get_video_downscale_enable(int *enable);									  
+unsigned long redcloud_get_video_dst_size(void);
+unsigned long redcloud_get_video_position(void);
+unsigned long redcloud_get_video_color_key(void);
+unsigned long redcloud_get_video_color_key_mask(void);
+int redcloud_get_video_palette_entry(unsigned long index, unsigned long *palette);
+int redcloud_get_video_color_key_src(void);
+int redcloud_get_video_filter(void);
+int redcloud_get_video_cursor(unsigned long *key, unsigned long *mask, unsigned short *select_color2,
+						 unsigned long *color1, unsigned short *color2);
+unsigned long redcloud_read_crc(void);
+unsigned long redcloud_read_crc32(void);
+unsigned long redcloud_read_window_crc(int source, unsigned short x, unsigned short y,
+								  unsigned short width, unsigned short height, int crc32);
+
+void redcloud_get_alpha_enable(int *enable);
+void redcloud_get_alpha_size(unsigned short *x, unsigned short *y, 
+	unsigned short *width, unsigned short *height);
+void redcloud_get_alpha_value(unsigned char *alpha, char *delta);
+void redcloud_get_alpha_priority(int *priority);
+void redcloud_get_alpha_color(unsigned long *color);
+int redcloud_get_video_request(short *x, short *y);
+#endif
+#endif
+
+/*--------------*/
+/* VIP ROUTINES */
+/*--------------*/
+
+#if GFX_VIP_SC1200
+
+/* DYNAMIC ROUTINES */
+
+#if GFX_VIP_DYNAMIC
+int sc1200_set_vip_enable(int enable);
+int sc1200_set_vip_capture_run_mode(int mode);
+int sc1200_set_vip_base(unsigned long even, unsigned long odd);
+int sc1200_set_vip_pitch(unsigned long pitch);
+int sc1200_set_vip_mode(int mode);
+int sc1200_set_vbi_enable(int enable);
+int sc1200_set_vbi_mode(int mode);
+int sc1200_set_vbi_base(unsigned long even, unsigned long odd);
+int sc1200_set_vbi_pitch(unsigned long pitch);
+int sc1200_set_vbi_direct(unsigned long even_lines, unsigned long odd_lines);
+int sc1200_set_vbi_interrupt(int enable);
+int sc1200_set_vip_bus_request_threshold_high(int enable);
+int sc1200_set_vip_last_line(int last_line);
+int sc1200_test_vip_odd_field(void);
+int sc1200_test_vip_bases_updated(void);
+int sc1200_test_vip_fifo_overflow(void);
+int sc1200_get_vip_line(void);
+int sc1200_get_vip_enable(void);
+unsigned long sc1200_get_vip_base(int odd);
+unsigned long sc1200_get_vip_pitch(void);
+int sc1200_get_vip_mode(void);
+int sc1200_get_vbi_enable(void);
+int sc1200_get_vbi_mode(void);
+unsigned long sc1200_get_vbi_base(int odd);
+unsigned long sc1200_get_vbi_pitch(void);
+unsigned long sc1200_get_vbi_direct(int odd);
+int sc1200_get_vbi_interrupt(void);
+int sc1200_get_vip_bus_request_threshold_high(void);
+#endif
+#endif
+
+/* DECODER ROUTINES */
+
+#if GFX_DECODER_SAA7114
+
+/* PRIVATE ROUTINES */
+
+int saa7114_write_reg(unsigned char reg, unsigned char val);
+int saa7114_read_reg(unsigned char reg, unsigned char * val);
+
+/* DYNAMIC ROUTINES */
+
+#if GFX_DECODER_DYNAMIC
+int saa7114_set_decoder_defaults(void);
+int saa7114_set_decoder_analog_input(unsigned char input);
+int saa7114_set_decoder_brightness(unsigned char brightness);
+int saa7114_set_decoder_contrast(unsigned char contrast);
+int saa7114_set_decoder_hue(char hue);
+int saa7114_set_decoder_saturation(unsigned char saturation);
+int saa7114_set_decoder_input_offset(unsigned short x, unsigned short y);
+int saa7114_set_decoder_input_size(unsigned short width, unsigned short height);
+int saa7114_set_decoder_output_size(unsigned short width, unsigned short height);
+int saa7114_set_decoder_scale(unsigned short srcw, unsigned short srch, 
+	unsigned short dstw, unsigned short dsth);
+int saa7114_set_decoder_vbi_format(int start, int end, int format);
+int saa7114_set_decoder_vbi_enable(int enable);
+int saa7114_set_decoder_vbi_upscale(void);
+int saa7114_set_decoder_TV_standard(TVStandardType TVStandard);
+int saa7114_set_decoder_luminance_filter(unsigned char lufi);
+int saa7114_decoder_software_reset(void);
+int saa7114_decoder_detect_macrovision(void);
+int saa7114_decoder_detect_video(void);
+unsigned char saa7114_get_decoder_brightness(void);
+unsigned char saa7114_get_decoder_contrast(void);
+char saa7114_get_decoder_hue(void);
+unsigned char saa7114_get_decoder_saturation(void);
+unsigned long saa7114_get_decoder_input_offset(void);
+unsigned long saa7114_get_decoder_input_size(void);
+unsigned long saa7114_get_decoder_output_size(void);
+int saa7114_get_decoder_vbi_format(int line);
+#endif
+#endif
+
+/* ACCESS I2C ROUTINES */
+
+#if GFX_I2C_ACCESS
+
+#if GFX_I2C_DYNAMIC
+int acc_i2c_reset(unsigned char busnum, short adr, char freq);
+int acc_i2c_write(unsigned char busnum, unsigned char chipadr, unsigned char subadr, 
+	unsigned char bytes, unsigned char * data);
+int acc_i2c_read(unsigned char busnum, unsigned char chipadr, unsigned char subadr, 
+	unsigned char bytes, unsigned char * data);
+int acc_i2c_select_gpio(int clock, int data);
+int acc_i2c_init(void);
+void acc_i2c_cleanup(void);
+#endif
+#endif
+
+/* GPIO I2C ROUTINES */
+
+#if GFX_I2C_GPIO
+
+#if GFX_I2C_DYNAMIC
+int gpio_i2c_reset(unsigned char busnum, short adr, char freq);
+int gpio_i2c_write(unsigned char busnum, unsigned char chipadr, unsigned char subadr, 
+	unsigned char bytes, unsigned char * data);
+int gpio_i2c_read(unsigned char busnum, unsigned char chipadr, unsigned char subadr, 
+	unsigned char bytes, unsigned char * data);
+int gpio_i2c_select_gpio(int clock, int data);
+int gpio_i2c_init(void);
+void gpio_i2c_cleanup(void);
+#endif
+#endif
+
+/* TV ROUTINES */
+
+#if GFX_TV_SC1200
+
+#if GFX_TV_DYNAMIC
+int sc1200_set_tv_format(TVStandardType format, GfxOnTVType resolution);
+int sc1200_set_tv_output(int output);
+int sc1200_set_tv_enable(int enable);
+int sc1200_set_tv_flicker_filter(int ff);
+int sc1200_set_tv_sub_carrier_reset(int screset);
+int sc1200_set_tv_vphase(int vphase);
+int sc1200_set_tv_YC_delay(int delay);
+int sc1200_set_tvenc_reset_interval(int interval);
+int sc1200_set_tv_cc_enable(int enable);
+int sc1200_set_tv_cc_data(unsigned char data1, unsigned char data2);
+int sc1200_set_tv_display(int width, int height);
+int sc1200_test_tvout_odd_field(void);
+int sc1200_test_tvenc_odd_field(void);
+int sc1200_set_tv_field_status_invert(int enable);
+int sc1200_get_tv_vphase(void);
+int sc1200_get_tv_enable(unsigned int *p_on);
+int sc1200_get_tv_output(void);
+int sc1200_get_tv_mode_count(TVStandardType format);
+int sc1200_get_tv_display_mode (int *width, int *height, int *bpp, int *hz);
+int sc1200_get_tv_display_mode_frequency (unsigned short width, unsigned short height, TVStandardType format, int *frequency);
+int sc1200_is_tv_display_mode_supported (unsigned short width, unsigned short height, TVStandardType format);
+unsigned char cc_add_parity_bit(unsigned char data);
+
+#endif
+#endif
+
+
+/* FS450 ROUTINES */
+
+#if GFX_TV_FS451
+
+#if GFX_TV_DYNAMIC
+int fs450_set_tv_format(TVStandardType format, GfxOnTVType resolution);
+int fs450_set_tv_output(int output);
+int fs450_set_tv_enable(int enable);
+int fs450_get_tv_standard(unsigned long *p_standard);
+int fs450_get_available_tv_standards(unsigned long *p_standards);
+int fs450_set_tv_standard(unsigned long standard);
+int fs450_get_tv_vga_mode(unsigned long *p_vga_mode);
+int fs450_get_available_tv_vga_modes(unsigned long *p_vga_modes);
+int fs450_set_tv_vga_mode(unsigned long vga_mode);
+int fs450_get_tvout_mode(unsigned long *p_tvout_mode);
+int fs450_set_tvout_mode(unsigned long tvout_mode);
+int fs450_get_sharpness(int *p_sharpness);
+int fs450_set_sharpness(int sharpness);
+int fs450_get_flicker_filter(int *p_flicker);
+int fs450_set_flicker_filter(int flicker);
+int fs450_get_overscan(int *p_x, int *p_y);
+int fs450_set_overscan(int x, int y);
+int fs450_get_position(int *p_x, int *p_y);
+int fs450_set_position(int x, int y);
+int fs450_get_color(int *p_color);
+int fs450_set_color(int color);
+int fs450_get_brightness(int *p_brightness);
+int fs450_set_brightness(int brightness);
+int fs450_get_contrast(int *p_contrast);
+int fs450_set_contrast(int constrast);
+int fs450_get_yc_filter(unsigned int *p_yc_filter);
+int fs450_set_yc_filter(unsigned int yc_filter);
+int fs450_get_aps_trigger_bits(unsigned int *p_trigger_bits);
+int fs450_set_aps_trigger_bits(unsigned int trigger_bits);
+#endif
+#endif
diff -uNr linux-2.4.31/drivers/video/nsc/gfx/gfx_regs.h linux-fb/drivers/video/nsc/gfx/gfx_regs.h
--- linux-2.4.31/drivers/video/nsc/gfx/gfx_regs.h	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/gfx/gfx_regs.h	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,1626 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * This header file contains the graphics register definitions.
+ * </DOC_AMD_STD>
+ */
+
+/*----------------------------------*/
+/*  FIRST GENERATION GRAPHICS UNIT  */
+/*----------------------------------*/
+
+#define GP_DST_XCOOR			0x8100		/* x destination origin		*/
+#define GP_DST_YCOOR			0x8102		/* y destination origin		*/
+#define GP_WIDTH				0x8104		/* pixel width				*/
+#define GP_HEIGHT				0x8106		/* pixel height				*/
+#define GP_SRC_XCOOR			0x8108		/* x source origin			*/
+#define GP_SRC_YCOOR			0x810A		/* y source origin			*/
+
+#define GP_VECTOR_LENGTH		0x8104		/* vector length			*/
+#define GP_INIT_ERROR			0x8106		/* vector initial error		*/
+#define GP_AXIAL_ERROR			0x8108		/* axial error increment	*/
+#define GP_DIAG_ERROR			0x810A		/* diagonal error increment */
+
+#define GP_SRC_COLOR_0			0x810C		/* source color 0			*/
+#define GP_SRC_COLOR_1			0x810E		/* source color 1			*/
+#define GP_PAT_COLOR_0			0x8110		/* pattern color 0          */
+#define GP_PAT_COLOR_1			0x8112		/* pattern color 1          */
+#define GP_PAT_COLOR_2			0x8114		/* pattern color 2          */
+#define GP_PAT_COLOR_3			0x8116		/* pattern color 3          */
+#define GP_PAT_DATA_0			0x8120		/* bits 31:0 of pattern		*/
+#define GP_PAT_DATA_1			0x8124		/* bits 63:32 of pattern	*/
+#define GP_PAT_DATA_2			0x8128		/* bits 95:64 of pattern	*/
+#define GP_PAT_DATA_3			0x812C		/* bits 127:96 of pattern	*/
+
+#define GP_VGA_WRITE			0x8140		/* VGA write path control   */
+#define GP_VGA_READ				0x8144		/* VGA read path control    */
+
+#define GP_RASTER_MODE			0x8200		/* raster operation			*/
+#define GP_VECTOR_MODE			0x8204		/* vector mode register		*/
+#define GP_BLIT_MODE			0x8208		/* blit mode register		*/
+#define GP_BLIT_STATUS			0x820C		/* blit status register		*/
+
+#define GP_VGA_BASE				0x8210		/* VGA memory offset (x64K) */
+#define GP_VGA_LATCH			0x8214		/* VGA display latch        */
+
+/* "GP_VECTOR_MODE" BIT DEFINITIONS */
+
+#define VM_X_MAJOR				0x0000		/* X major vector			*/
+#define VM_Y_MAJOR				0x0001		/* Y major vector			*/
+#define VM_MAJOR_INC			0x0002		/* positive major axis step */
+#define VM_MINOR_INC			0x0004		/* positive minor axis step */
+#define VM_READ_DST_FB			0x0008		/* read destination data	*/
+
+/* "GP_RASTER_MODE" BIT DEFINITIONS */
+
+#define RM_PAT_DISABLE			0x0000		/* pattern is disabled		*/
+#define RM_PAT_MONO				0x0100		/* 1BPP pattern expansion	*/
+#define RM_PAT_DITHER			0x0200		/* 2BPP pattern expansion	*/
+#define RM_PAT_COLOR			0x0300		/* 8BPP or 16BPP pattern	*/
+#define RM_PAT_MASK				0x0300		/* mask for pattern mode	*/
+#define RM_PAT_TRANSPARENT		0x0400		/* transparent 1BPP pattern	*/
+#define RM_SRC_TRANSPARENT		0x0800		/* transparent 1BPP source	*/
+
+/* "GP_BLIT_STATUS" BIT DEFINITIONS */
+
+#define BS_BLIT_BUSY			0x0001		/* blit engine is busy		*/
+#define BS_PIPELINE_BUSY		0x0002		/* graphics pipeline is busy*/
+#define BS_BLIT_PENDING			0x0004		/* blit pending				*/
+#define BC_FLUSH				0x0080		/* flush pipeline requests  */
+#define BC_8BPP					0x0000		/* 8BPP mode				*/
+#define BC_16BPP				0x0100		/* 16BPP mode				*/
+#define BC_FB_WIDTH_1024		0x0000		/* framebuffer width = 1024 */
+#define BC_FB_WIDTH_2048		0x0200		/* framebuffer width = 2048 */
+#define BC_FB_WIDTH_4096		0x0400		/* framebuffer width = 4096	*/
+
+/* "GP_BLIT_MODE" BIT DEFINITIONS */
+
+#define	BM_READ_SRC_NONE		0x0000		/* source foreground color	*/
+#define BM_READ_SRC_FB			0x0001		/* read source from FB		*/
+#define BM_READ_SRC_BB0			0x0002		/* read source from BB0		*/
+#define BM_READ_SRC_BB1			0x0003		/* read source from BB1		*/
+#define BM_READ_SRC_MASK		0x0003		/* read source mask			*/
+
+#define	BM_READ_DST_NONE		0x0000		/* no destination data		*/
+#define BM_READ_DST_BB0			0x0008		/* destination from BB0		*/
+#define BM_READ_DST_BB1			0x000C		/* destination from BB1		*/
+#define BM_READ_DST_FB0			0x0010		/* dest from FB (store BB0) */
+#define BM_READ_DST_FB1			0x0014		/* dest from FB (store BB1) */
+#define BM_READ_DST_MASK		0x001C		/* read destination mask	*/
+
+#define BM_WRITE_FB				0x0000		/* write to framebuffer		*/
+#define	BM_WRITE_MEM			0x0020		/* write to memory			*/
+#define BM_WRITE_MASK			0x0020		/* write mask				*/
+
+#define	BM_SOURCE_COLOR			0x0000		/* source is 8BPP or 16BPP	*/
+#define BM_SOURCE_EXPAND		0x0040		/* source is 1BPP			*/
+#define BM_SOURCE_TEXT			0x00C0		/* source is 1BPP text		*/
+#define BM_SOURCE_MASK			0x00C0		/* source mask				*/
+
+#define BM_REVERSE_Y			0x0100		/* reverse Y direction		*/
+
+/*---------------------------------------*/
+/*  FIRST GENERATION DISPLAY CONTROLLER  */
+/*---------------------------------------*/
+
+#define DC_UNLOCK				0x8300		/* lock register			*/
+#define DC_GENERAL_CFG			0x8304		/* config registers...		*/
+#define DC_TIMING_CFG			0x8308
+#define DC_OUTPUT_CFG			0x830C
+
+#define DC_FB_ST_OFFSET			0x8310		/* framebuffer start offset */
+#define DC_CB_ST_OFFSET			0x8314		/* compression start offset */
+#define DC_CURS_ST_OFFSET		0x8318		/* cursor start offset		*/
+#define DC_ICON_ST_OFFSET		0x831C		/* icon start offset		*/
+#define DC_VID_ST_OFFSET		0x8320		/* video start offset		*/
+#define DC_LINE_DELTA			0x8324		/* fb and cb skip counts	*/
+#define DC_BUF_SIZE				0x8328		/* fb and cb line size		*/
+
+#define DC_H_TIMING_1			0x8330		/* horizontal timing...		*/
+#define DC_H_TIMING_2			0x8334
+#define DC_H_TIMING_3			0x8338
+#define DC_FP_H_TIMING			0x833C
+
+#define DC_V_TIMING_1			0x8340		/* vertical timing...		*/
+#define DC_V_TIMING_2			0x8344
+#define DC_V_TIMING_3			0x8348
+#define DC_FP_V_TIMING			0x834C
+
+#define DC_CURSOR_X				0x8350		/* cursor x position		*/
+#define DC_ICON_X				0x8354		/* HACK - 1.3 definition	*/
+#define DC_V_LINE_CNT			0x8354		/* vertical line counter	*/
+#define DC_CURSOR_Y				0x8358		/* cursor y position		*/
+#define DC_ICON_Y				0x835C		/* HACK - 1.3 definition	*/
+#define DC_SS_LINE_CMP			0x835C		/* line compare value		*/
+#define DC_CURSOR_COLOR			0x8360		/* cursor colors			*/
+#define DC_ICON_COLOR			0x8364		/* icon colors				*/
+#define DC_BORDER_COLOR			0x8368		/* border color				*/
+#define DC_PAL_ADDRESS			0x8370		/* palette address			*/
+#define DC_PAL_DATA				0x8374		/* palette data				*/
+#define DC_DFIFO_DIAG			0x8378		/* display FIFO diagnostic	*/
+#define DC_CFIFO_DIAG			0x837C		/* compression FIF0 diagnostic	*/
+
+/* PALETTE LOCATIONS */
+
+#define PAL_CURSOR_COLOR_0		0x100
+#define PAL_CURSOR_COLOR_1		0x101
+#define PAL_ICON_COLOR_0		0x102
+#define PAL_ICON_COLOR_1		0x103
+#define PAL_OVERSCAN_COLOR		0x104
+
+/* UNLOCK VALUE */
+
+#define DC_UNLOCK_VALUE		0x00004758		/* used to unlock DC regs	*/
+
+/* "DC_GENERAL_CFG" BIT DEFINITIONS */
+
+#define DC_GCFG_DFLE		0x00000001		/* display FIFO load enable */
+#define DC_GCFG_CURE		0x00000002		/* cursor enable			*/
+#define DC_GCFG_VCLK_DIV	0x00000004		/* vid clock divisor		*/
+#define DC_GCFG_PLNO		0x00000004		/* planar offset LSB		*/
+#define DC_GCFG_PPC			0x00000008		/* pixel pan compatibility  */
+#define DC_GCFG_CMPE		0x00000010		/* compression enable       */
+#define DC_GCFG_DECE		0x00000020		/* decompression enable     */
+#define DC_GCFG_DCLK_MASK	0x000000C0		/* dotclock multiplier      */
+#define DC_GCFG_DCLK_POS	6				/* dotclock multiplier      */
+#define DC_GCFG_DFHPSL_MASK	0x00000F00		/* FIFO high-priority start */
+#define DC_GCFG_DFHPSL_POS	8				/* FIFO high-priority start */
+#define DC_GCFG_DFHPEL_MASK	0x0000F000		/* FIFO high-priority end   */
+#define DC_GCFG_DFHPEL_POS	12				/* FIFO high-priority end   */
+#define DC_GCFG_CIM_MASK	0x00030000		/* compressor insert mode   */
+#define DC_GCFG_CIM_POS		16				/* compressor insert mode   */
+#define DC_GCFG_FDTY		0x00040000		/* frame dirty mode         */
+#define DC_GCFG_RTPM		0x00080000		/* real-time perf. monitor  */
+#define DC_GCFG_DAC_RS_MASK	0x00700000		/* DAC register selects     */
+#define DC_GCFG_DAC_RS_POS	20				/* DAC register selects     */
+#define DC_GCFG_CKWR		0x00800000		/* clock write              */
+#define DC_GCFG_LDBL		0x01000000		/* line double              */
+#define DC_GCFG_DIAG		0x02000000		/* FIFO diagnostic mode     */
+#define DC_GCFG_CH4S		0x04000000      /* sparse refresh mode		*/
+#define DC_GCFG_SSLC		0x08000000		/* enable line compare		*/
+#define DC_GCFG_VIDE		0x10000000		/* video enable			    */
+#define DC_GCFG_DFCK		0x20000000		/* divide flat-panel clock - rev 2.3 down */
+#define DC_GCFG_VRDY		0x20000000		/* video port speed - rev 2.4 up  */
+#define DC_GCFG_DPCK		0x40000000		/* divide pixel clock       */
+#define DC_GCFG_DDCK		0x80000000		/* divide dot clock         */
+
+/* "DC_TIMING_CFG" BIT DEFINITIONS */
+
+#define DC_TCFG_FPPE		0x00000001		/* flat-panel power enable  */
+#define DC_TCFG_HSYE		0x00000002		/* horizontal sync enable   */
+#define DC_TCFG_VSYE		0x00000004		/* vertical sync enable     */
+#define DC_TCFG_BLKE		0x00000008		/* blank enable				*/
+#define DC_TCFG_DDCK		0x00000010		/* DDC clock                */
+#define DC_TCFG_TGEN		0x00000020		/* timing generator enable  */
+#define DC_TCFG_VIEN		0x00000040		/* vertical interrupt enable*/
+#define DC_TCFG_BLNK		0x00000080		/* blink enable             */
+#define DC_TCFG_CHSP		0x00000100		/* horizontal sync polarity */
+#define DC_TCFG_CVSP		0x00000200		/* vertical sync polarity   */
+#define DC_TCFG_FHSP		0x00000400		/* panel horz sync polarity */
+#define DC_TCFG_FVSP		0x00000800		/* panel vert sync polarity */
+#define DC_TCFG_FCEN		0x00001000		/* flat-panel centering     */
+#define DC_TCFG_CDCE		0x00002000		/* HACK - 1.3 definition	*/
+#define DC_TCFG_PLNR		0x00002000		/* planar mode enable		*/
+#define DC_TCFG_INTL		0x00004000		/* interlace scan           */
+#define DC_TCFG_PXDB		0x00008000		/* pixel double             */
+#define DC_TCFG_BKRT		0x00010000		/* blink rate               */
+#define DC_TCFG_PSD_MASK	0x000E0000		/* power sequence delay     */
+#define DC_TCFG_PSD_POS		17				/* power sequence delay     */
+#define DC_TCFG_DDCI		0x08000000		/* DDC input (RO)           */
+#define DC_TCFG_SENS		0x10000000		/* monitor sense (RO)       */
+#define DC_TCFG_DNA			0x20000000		/* display not active (RO)  */
+#define DC_TCFG_VNA			0x40000000		/* vertical not active (RO) */
+#define DC_TCFG_VINT		0x80000000		/* vertical interrupt (RO)  */
+
+/* "DC_OUTPUT_CFG" BIT DEFINITIONS */
+
+#define DC_OCFG_8BPP		0x00000001		/* 8/16 bpp select          */
+#define DC_OCFG_555			0x00000002		/* 16 bpp format            */
+#define DC_OCFG_PCKE		0x00000004		/* PCLK enable              */
+#define DC_OCFG_FRME		0x00000008		/* frame rate mod enable    */
+#define DC_OCFG_DITE		0x00000010		/* dither enable            */
+#define DC_OCFG_2PXE		0x00000020		/* 2 pixel enable           */
+#define DC_OCFG_2XCK		0x00000040		/* 2 x pixel clock          */
+#define DC_OCFG_2IND		0x00000080		/* 2 index enable           */
+#define DC_OCFG_34ADD		0x00000100		/* 3- or 4-bit add          */
+#define DC_OCFG_FRMS		0x00000200		/* frame rate mod select    */
+#define DC_OCFG_CKSL		0x00000400		/* clock select             */
+#define DC_OCFG_PRMP		0x00000800		/* palette re-map           */
+#define DC_OCFG_PDEL		0x00001000		/* panel data enable low    */
+#define DC_OCFG_PDEH		0x00002000		/* panel data enable high   */
+#define DC_OCFG_CFRW		0x00004000		/* comp line buffer r/w sel */
+#define DC_OCFG_DIAG		0x00008000		/* comp line buffer diag    */
+
+#define MC_MEM_CNTRL1       0x00008400
+#define MC_DR_ADD			0x00008418
+#define MC_DR_ACC			0x0000841C
+
+/* MC_MEM_CNTRL1 BIT DEFINITIONS */
+
+#define MC_XBUSARB          0x00000008      /* 0 = GP priority < CPU priority */
+											/* 1 = GP priority = CPU priority */
+											/* GXm databook V2.0 is wrong ! */
+/*----------*/
+/*  CS5530  */
+/*----------*/
+
+/* CS5530 REGISTER DEFINITIONS */
+
+#define CS5530_VIDEO_CONFIG 		0x0000
+#define CS5530_DISPLAY_CONFIG       0x0004
+#define CS5530_VIDEO_X_POS          0x0008
+#define CS5530_VIDEO_Y_POS          0x000C
+#define CS5530_VIDEO_SCALE          0x0010
+#define CS5530_VIDEO_COLOR_KEY		0x0014
+#define CS5530_VIDEO_COLOR_MASK		0x0018
+#define CS5530_PALETTE_ADDRESS 		0x001C
+#define CS5530_PALETTE_DATA	 		0x0020
+#define CS5530_DOT_CLK_CONFIG       0x0024
+#define CS5530_CRCSIG_TFT_TV        0x0028
+
+/* "CS5530_VIDEO_CONFIG" BIT DEFINITIONS */
+
+#define CS5530_VCFG_VID_EN					0x00000001	
+#define CS5530_VCFG_VID_REG_UPDATE			0x00000002	
+#define CS5530_VCFG_VID_INP_FORMAT			0x0000000C	
+#define CS5530_VCFG_8_BIT_4_2_0				0x00000004
+#define CS5530_VCFG_16_BIT_4_2_0			0x00000008
+#define CS5530_VCFG_GV_SEL					0x00000010	
+#define CS5530_VCFG_CSC_BYPASS				0x00000020	
+#define CS5530_VCFG_X_FILTER_EN				0x00000040	
+#define CS5530_VCFG_Y_FILTER_EN				0x00000080	
+#define CS5530_VCFG_LINE_SIZE_LOWER_MASK	0x0000FF00	
+#define CS5530_VCFG_INIT_READ_MASK			0x01FF0000	
+#define CS5530_VCFG_EARLY_VID_RDY  			0x02000000	
+#define CS5530_VCFG_LINE_SIZE_UPPER			0x08000000	
+#define CS5530_VCFG_4_2_0_MODE				0x10000000	
+#define CS5530_VCFG_16_BIT_EN				0x20000000
+#define CS5530_VCFG_HIGH_SPD_INT			0x40000000
+
+/* "CS5530_DISPLAY_CONFIG" BIT DEFINITIONS */
+
+#define CS5530_DCFG_DIS_EN					0x00000001	
+#define CS5530_DCFG_HSYNC_EN				0x00000002	
+#define CS5530_DCFG_VSYNC_EN				0x00000004	
+#define CS5530_DCFG_DAC_BL_EN				0x00000008	
+#define CS5530_DCFG_DAC_PWDNX				0x00000020	
+#define CS5530_DCFG_FP_PWR_EN				0x00000040	
+#define CS5530_DCFG_FP_DATA_EN				0x00000080	
+#define CS5530_DCFG_CRT_HSYNC_POL 			0x00000100	
+#define CS5530_DCFG_CRT_VSYNC_POL 			0x00000200	
+#define CS5530_DCFG_FP_HSYNC_POL  			0x00000400	
+#define CS5530_DCFG_FP_VSYNC_POL  			0x00000800	
+#define CS5530_DCFG_XGA_FP		  			0x00001000	
+#define CS5530_DCFG_FP_DITH_EN				0x00002000	
+#define CS5530_DCFG_CRT_SYNC_SKW_MASK		0x0001C000
+#define CS5530_DCFG_CRT_SYNC_SKW_INIT		0x00010000
+#define CS5530_DCFG_PWR_SEQ_DLY_MASK		0x000E0000
+#define CS5530_DCFG_PWR_SEQ_DLY_INIT		0x00080000
+#define CS5530_DCFG_VG_CK					0x00100000
+#define CS5530_DCFG_GV_PAL_BYP				0x00200000
+#define CS5530_DCFG_DDC_SCL					0x00400000
+#define CS5530_DCFG_DDC_SDA					0x00800000
+#define CS5530_DCFG_DDC_OE					0x01000000
+#define CS5530_DCFG_16_BIT_EN				0x02000000
+
+
+/*----------*/
+/*  SC1200  */
+/*----------*/
+
+/* SC1200 VIDEO REGISTER DEFINITIONS */
+
+#define SC1200_VIDEO_CONFIG 				0x000
+#define SC1200_DISPLAY_CONFIG				0x004
+#define SC1200_VIDEO_X_POS					0x008
+#define SC1200_VIDEO_Y_POS					0x00C
+#define SC1200_VIDEO_UPSCALE				0x010
+#define SC1200_VIDEO_COLOR_KEY				0x014
+#define SC1200_VIDEO_COLOR_MASK				0x018
+#define SC1200_PALETTE_ADDRESS 				0x01C
+#define SC1200_PALETTE_DATA	 				0x020
+#define SC1200_VID_MISC						0x028
+#define SC1200_VID_CLOCK_SELECT				0x02C
+#define SC1200_VIDEO_DOWNSCALER_CONTROL     0x03C 
+#define SC1200_VIDEO_DOWNSCALER_COEFFICIENTS 0x40  
+#define SC1200_VID_CRC						0x044
+#define SC1200_DEVICE_ID					0x048
+#define SC1200_VID_ALPHA_CONTROL			0x04C
+#define SC1200_CURSOR_COLOR_KEY				0x050
+#define SC1200_CURSOR_COLOR_MASK			0x054
+#define SC1200_CURSOR_COLOR_1				0x058
+#define SC1200_CURSOR_COLOR_2				0x05C
+#define SC1200_ALPHA_XPOS_1					0x060
+#define SC1200_ALPHA_YPOS_1					0x064
+#define SC1200_ALPHA_COLOR_1				0x068
+#define SC1200_ALPHA_CONTROL_1				0x06C
+#define SC1200_ALPHA_XPOS_2					0x070
+#define SC1200_ALPHA_YPOS_2					0x074
+#define SC1200_ALPHA_COLOR_2				0x078
+#define SC1200_ALPHA_CONTROL_2				0x07C
+#define SC1200_ALPHA_XPOS_3					0x080
+#define SC1200_ALPHA_YPOS_3					0x084
+#define SC1200_ALPHA_COLOR_3				0x088
+#define SC1200_ALPHA_CONTROL_3				0x08C
+#define SC1200_VIDEO_REQUEST                0x090
+#define SC1200_ALPHA_WATCH 					0x094
+#define SC1200_VIDEO_DISPLAY_MODE           0x400
+#define SC1200_VIDEO_ODD_VBI_LINE_ENABLE    0x40C
+#define SC1200_VIDEO_EVEN_VBI_LINE_ENABLE   0x410
+#define SC1200_VIDEO_VBI_HORIZ_CONTROL      0x414
+#define SC1200_VIDEO_ODD_VBI_TOTAL_COUNT    0x418
+#define SC1200_VIDEO_EVEN_VBI_TOTAL_COUNT   0x41C
+#define SC1200_GENLOCK                      0x420
+#define SC1200_GENLOCK_DELAY                0x424
+#define SC1200_TVOUT_HORZ_TIM				0x800
+#define SC1200_TVOUT_HORZ_SYNC				0x804
+#define SC1200_TVOUT_VERT_SYNC				0x808
+#define SC1200_TVOUT_LINE_END				0x80C
+#define SC1200_TVOUT_VERT_DOWNSCALE			0x810 /* REV. A & B */
+#define SC1200_TVOUT_HORZ_PRE_ENCODER_SCALE 0x810 /* REV. C */
+#define SC1200_TVOUT_HORZ_SCALING			0x814
+#define SC1200_TVOUT_DEBUG                  0x818
+#define SC1200_TVENC_TIM_CTRL_1				0xC00
+#define SC1200_TVENC_TIM_CTRL_2				0xC04
+#define SC1200_TVENC_TIM_CTRL_3				0xC08
+#define SC1200_TVENC_SUB_FREQ				0xC0C
+#define SC1200_TVENC_DISP_POS				0xC10
+#define SC1200_TVENC_DISP_SIZE				0xC14
+#define SC1200_TVENC_CC_DATA				0xC18
+#define SC1200_TVENC_EDS_DATA				0xC1C
+#define SC1200_TVENC_CGMS_DATA				0xC20
+#define SC1200_TVENC_WSS_DATA				0xC24
+#define SC1200_TVENC_CC_CONTROL				0xC28
+#define SC1200_TVENC_DAC_CONTROL			0xC2C
+#define SC1200_TVENC_MV_CONTROL             0xC30
+
+/* "SC1200_VIDEO_CONFIG" BIT DEFINITIONS */
+
+#define SC1200_VCFG_VID_EN					0x00000001	
+#define SC1200_VCFG_VID_INP_FORMAT			0x0000000C	
+#define SC1200_VCFG_UYVY_FORMAT				0x00000000
+#define SC1200_VCFG_Y2YU_FORMAT				0x00000004
+#define SC1200_VCFG_YUYV_FORMAT				0x00000008
+#define SC1200_VCFG_YVYU_FORMAT				0x0000000C
+#define SC1200_VCFG_X_FILTER_EN				0x00000040	
+#define SC1200_VCFG_Y_FILTER_EN				0x00000080	
+#define SC1200_VCFG_LINE_SIZE_LOWER_MASK	0x0000FF00	
+#define SC1200_VCFG_INIT_READ_MASK			0x01FF0000	
+#define SC1200_VCFG_LINE_SIZE_UPPER			0x08000000	
+#define SC1200_VCFG_4_2_0_MODE				0x10000000	
+
+/* "SC1200_DISPLAY_CONFIG" BIT DEFINITIONS */
+
+#define SC1200_DCFG_DIS_EN					0x00000001	
+#define SC1200_DCFG_HSYNC_EN				0x00000002	
+#define SC1200_DCFG_VSYNC_EN				0x00000004	
+#define SC1200_DCFG_DAC_BL_EN				0x00000008	
+#define SC1200_DCFG_FP_PWR_EN				0x00000040
+#define SC1200_DCFG_FP_DATA_EN				0x00000080	
+#define SC1200_DCFG_CRT_HSYNC_POL 			0x00000100	
+#define SC1200_DCFG_CRT_VSYNC_POL 			0x00000200	
+#define SC1200_DCFG_CRT_SYNC_SKW_MASK		0x0001C000
+#define SC1200_DCFG_CRT_SYNC_SKW_INIT		0x00010000
+#define SC1200_DCFG_PWR_SEQ_DLY_MASK		0x000E0000
+#define SC1200_DCFG_PWR_SEQ_DLY_INIT		0x00080000
+#define SC1200_DCFG_VG_CK					0x00100000
+#define SC1200_DCFG_GV_PAL_BYP				0x00200000
+#define SC1200_DCFG_DDC_SCL					0x00400000
+#define SC1200_DCFG_DDC_SDA					0x00800000
+#define SC1200_DCFG_DDC_OE					0x01000000
+
+/* "SC1200_VID_MISC" BIT DEFINITIONS */
+
+#define SC1200_GAMMA_BYPASS_BOTH            0x00000001
+#define SC1200_DAC_POWER_DOWN               0x00000400
+#define SC1200_ANALOG_POWER_DOWN            0x00000800
+#define SC1200_PLL_POWER_NORMAL             0x00001000
+
+/* "SC1200_VIDEO_DOWNSCALER_CONTROL" BIT DEFINITIONS */
+
+#define SC1200_VIDEO_DOWNSCALE_ENABLE       0x00000001
+#define SC1200_VIDEO_DOWNSCALE_FACTOR_POS   1
+#define SC1200_VIDEO_DOWNSCALE_FACTOR_MASK  0x0000001E
+#define SC1200_VIDEO_DOWNSCALE_TYPE_A       0x00000000
+#define SC1200_VIDEO_DOWNSCALE_TYPE_B       0x00000040
+#define SC1200_VIDEO_DOWNSCALE_TYPE_MASK    0x00000040
+
+/* "SC1200_VIDEO_DOWNSCALER_COEFFICIENTS" BIT DEFINITIONS */
+
+#define SC1200_VIDEO_DOWNSCALER_COEF1_POS   0
+#define SC1200_VIDEO_DOWNSCALER_COEF2_POS   8
+#define SC1200_VIDEO_DOWNSCALER_COEF3_POS   16
+#define SC1200_VIDEO_DOWNSCALER_COEF4_POS   24
+#define SC1200_VIDEO_DOWNSCALER_COEF_MASK   0xF
+
+/* VIDEO DE-INTERLACING AND ALPHA CONTROL (REGISTER 0x4C) */
+
+#define SC1200_VERTICAL_SCALER_SHIFT_MASK   0x00000007
+#define SC1200_VERTICAL_SCALER_SHIFT_INIT   0x00000004
+#define SC1200_VERTICAL_SCALER_SHIFT_EN     0x00000010
+#define SC1200_TOP_LINE_IN_ODD              0x00000040
+#define SC1200_NO_CK_OUTSIDE_ALPHA          0x00000100
+#define SC1200_VIDEO_IS_INTERLACED          0x00000200
+#define SC1200_CSC_VIDEO_YUV_TO_RGB         0x00000400
+#define SC1200_CSC_GFX_RGB_TO_YUV           0x00000800
+#define SC1200_VIDEO_INPUT_IS_RGB           0x00002000
+#define SC1200_VIDEO_LINE_OFFSET_ODD        0x00001000
+#define SC1200_ALPHA1_PRIORITY_POS			16
+#define SC1200_ALPHA1_PRIORITY_MASK			0x00030000
+#define SC1200_ALPHA2_PRIORITY_POS			18
+#define SC1200_ALPHA2_PRIORITY_MASK			0x000C0000
+#define SC1200_ALPHA3_PRIORITY_POS			20
+#define SC1200_ALPHA3_PRIORITY_MASK			0x00300000
+
+/* VIDEO CURSOR COLOR KEY DEFINITIONS (REGISTER 0x50) */
+
+#define SC1200_CURSOR_COLOR_KEY_OFFSET_POS  24
+#define SC1200_CURSOR_COLOR_BITS            23
+#define SC1200_COLOR_MASK                   0x00FFFFFF /* 24 significant bits */
+
+/* ALPHA COLOR BIT DEFINITION (REGISTERS 0x68, 0x78, AND 0x88) */
+
+#define SC1200_ALPHA_COLOR_ENABLE           0x01000000
+
+/* ALPHA CONTROL BIT DEFINITIONS (REGISTERS 0x6C, 0x7C, AND 0x8C) */
+
+#define SC1200_ACTRL_WIN_ENABLE				0x00010000
+#define SC1200_ACTRL_LOAD_ALPHA				0x00020000
+
+/* VIDEO REQUEST DEFINITIONS (REGISTER 0x90) */
+
+#define SC1200_VIDEO_Y_REQUEST_POS          0
+#define SC1200_VIDEO_X_REQUEST_POS          16
+#define SC1200_VIDEO_REQUEST_MASK           0x00000FFF
+
+/* VIDEO DISPLAY MODE (REGISTER 0x400) */
+
+#define SC1200_VIDEO_SOURCE_MASK            0x00000003
+#define SC1200_VIDEO_SOURCE_GX1             0x00000000
+#define SC1200_VIDEO_SOURCE_DVIP            0x00000002
+#define SC1200_VBI_SOURCE_MASK              0x00000004
+#define SC1200_VBI_SOURCE_DVIP              0x00000000
+#define SC1200_VBI_SOURCE_GX1               0x00000004
+
+/* ODD/EVEN VBI LINE ENABLE (REGISTERS 0x40C, 0x410) */
+
+#define SC1200_VIDEO_VBI_LINE_ENABLE_MASK   0x00FFFFFC
+#define SC1200_VIDEO_ALL_ACTIVE_IS_VBI      0x01000000
+#define SC1200_VIDEO_VBI_LINE_OFFSET_POS    25
+#define SC1200_VIDEO_VBI_LINE_OFFSET_MASK   0x3E000000
+
+/* ODD/EVEN VBI TOTAL COUNT (REGISTERS 0x418, 0x41C) */
+
+#define SC1200_VIDEO_VBI_TOTAL_COUNT_MASK   0x000FFFFF
+
+/* GENLOCK BIT DEFINITIONS */
+
+#define SC1200_GENLOCK_SINGLE_ENABLE              0x00000001
+#define SC1200_GENLOCK_FIELD_SYNC_ENABLE          0x00000001
+#define SC1200_GENLOCK_CONTINUOUS_ENABLE          0x00000002
+#define SC1200_GENLOCK_GX_VSYNC_FALLING_EDGE      0x00000004
+#define SC1200_GENLOCK_VIP_VSYNC_FALLING_EDGE     0x00000008
+#define SC1200_GENLOCK_TIMEOUT_ENABLE             0x00000010
+#define SC1200_GENLOCK_TVENC_RESET_EVEN_FIELD     0x00000020
+#define SC1200_GENLOCK_TVENC_RESET_BEFORE_DELAY   0x00000040
+#define SC1200_GENLOCK_TVENC_RESET_ENABLE         0x00000080
+#define SC1200_GENLOCK_SYNC_TO_TVENC              0x00000100
+#define SC1200_GENLOCK_DELAY_MASK                 0x001FFFFF
+
+/* TVOUT HORIZONTAL PRE ENCODER SCALE BIT DEFINITIONS */
+
+#define SC1200_TVOUT_YC_DELAY_MASK                0x00C00000
+#define SC1200_TVOUT_YC_DELAY_NONE                0x00000000
+#define SC1200_TVOUT_Y_DELAY_ONE_PIXEL            0x00400000
+#define SC1200_TVOUT_C_DELAY_ONE_PIXEL            0x00800000
+#define SC1200_TVOUT_C_DELAY_TWO_PIXELS           0x00C00000
+
+/* TVOUT HORIZONTAL SCALING/CONTROL BIT DEFINITIONS */
+
+#define SC1200_TVOUT_FLICKER_FILTER_MASK               0x60000000
+#define SC1200_TVOUT_FLICKER_FILTER_FOURTH_HALF_FOURTH 0x00000000
+#define SC1200_TVOUT_FLICKER_FILTER_HALF_ONE_HALF      0x20000000
+#define SC1200_TVOUT_FLICKER_FILTER_DISABLED           0x40000000
+#define SC1200_TVENC_EXTERNAL_RESET_INTERVAL_MASK      0x0F000000
+#define SC1200_TVENC_EXTERNAL_RESET_EVERY_ODD_FIELD    0x00000000
+#define SC1200_TVENC_EXTERNAL_RESET_EVERY_EVEN_FIELD   0x02000000
+#define SC1200_TVENC_EXTERNAL_RESET_NEXT_ODD_FIELD     0x05000000
+#define SC1200_TVENC_EXTERNAL_RESET_NEXT_EVEN_FIELD    0x07000000
+#define SC1200_TVENC_EXTERNAL_RESET_EVERY_FIELD        0x0E000000
+#define SC1200_TVENC_EXTERNAL_RESET_EVERY_X_ODD_FIELDS  0x08000000
+#define SC1200_TVENC_EXTERNAL_RESET_EVERY_X_EVEN_FIELDS 0x0A000000
+
+/* TVOUT DEBUG BIT DEFINITIONS */
+
+#define SC1200_TVOUT_FIELD_STATUS_EVEN         0x00000040
+#define SC1200_TVOUT_FIELD_STATUS_TV           0x00000080
+#define SC1200_TVOUT_CRT_VSYNC_STATUS_TRAILING 0x00000100
+#define SC1200_TVOUT_FIELD_STATUS_INVERT      0x00000200
+#define SC1200_TVOUT_CONVERTER_INTERPOLATION   0x00000400
+
+/* TVENC TIMING/CONTROL 1 BIT DEFINITIONS (REGISTER 0xC00) */
+
+#define SC1200_TVENC_VPHASE_MASK                          0x001FF800
+#define SC1200_TVENC_VPHASE_POS                           11
+#define SC1200_TVENC_SUB_CARRIER_RESET_MASK               0x30000000
+#define SC1200_TVENC_SUB_CARRIER_RESET_NEVER              0x00000000
+#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_TWO_LINES    0x10000000
+#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_TWO_FRAMES   0x20000000
+#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_FOUR_FRAMES  0x30000000
+#define SC1200_TVENC_VIDEO_TIMING_ENABLE                  0x80000000
+
+/* TVENC TIMING/CONTROL 2 BIT DEFINITIONS (REGISTER 0xC04) */
+
+#define SC1200_TVENC_OUTPUT_YCBCR                         0x40000000
+#define SC1200_TVENC_CFS_MASK                             0x00030000
+#define SC1200_TVENC_CFS_BYPASS                           0x00000000
+#define SC1200_TVENC_CFS_CVBS                             0x00020000
+#define SC1200_TVENC_CFS_SVIDEO                           0x00030000
+
+/* TVENC TIMING/CONTROL 3 BIT DEFINITIONS (REGISTER 0xC08) */
+
+#define SC1200_TVENC_CS                                   0x00000001
+#define SC1200_TVENC_SYNCMODE_MASK                        0x00000006
+#define SC1200_TVENC_SYNC_ON_GREEN                        0x00000002
+#define SC1200_TVENC_SYNC_ON_CVBS                         0x00000004
+#define SC1200_TVENC_CM                                   0x00000008
+
+/* TVENC DAC CONTROL BIT DEFINITIONS (REGISTER 0xC2C) */
+#define SC1200_TVENC_TRIM_MASK	               0x00000007
+#define SC1200_TVENC_POWER_DOWN	               0x00000020
+
+/* TVENC MV CONTROL BIT DEFINITIONS (REGISTER 0xC30) */
+#define SC1200_TVENC_MV_ENABLE                 0xBE
+
+/* SC1200 VIP REGISTER DEFINITIONS */
+
+#define SC1200_VIP_CONFIG					0x00000000
+#define SC1200_VIP_CONTROL					0x00000004
+#define SC1200_VIP_STATUS					0x00000008
+#define SC1200_VIP_CURRENT_LINE				0x00000010
+#define SC1200_VIP_LINE_TARGET				0x00000014
+#define SC1200_ODD_DIRECT_VBI_LINE_ENABLE   0x00000018
+#define SC1200_EVEN_DIRECT_VBI_LINE_ENABLE  0x0000001C
+#define SC1200_VIP_ODD_BASE					0x00000020
+#define SC1200_VIP_EVEN_BASE				0x00000024
+#define SC1200_VIP_PITCH					0x00000028
+#define SC1200_VBI_ODD_BASE					0x00000040
+#define SC1200_VBI_EVEN_BASE				0x00000044
+#define SC1200_VBI_PITCH					0x00000048
+
+/* "SC1200_VIP_CONFIG" BIT DEFINITIONS */
+
+#define SC1200_VIP_MODE_MASK                0x00000003
+#define	SC1200_VIP_MODE_C       			0x00000002
+#define SC1200_VBI_ANCILLARY_TO_MEMORY      0x000C0000
+#define SC1200_VBI_TASK_A_TO_MEMORY         0x00140000
+#define SC1200_VBI_TASK_B_TO_MEMORY         0x00240000
+#define SC1200_VIP_BUS_REQUEST_THRESHOLD    0x00400000
+
+/* "SC1200_VIP_CONTROL" BIT DEFINITIONS */
+
+#define SC1200_CAPTURE_RUN_MODE_MASK        0x00000003
+#define SC1200_CAPTURE_RUN_MODE_STOP_LINE   0x00000000
+#define SC1200_CAPTURE_RUN_MODE_STOP_FIELD  0x00000001
+#define SC1200_CAPTURE_RUN_MODE_START       0x00000003
+#define	SC1200_VIP_DATA_CAPTURE_EN			0x00000100
+#define	SC1200_VIP_VBI_CAPTURE_EN			0x00000200
+#define	SC1200_VIP_VBI_FIELD_INTERRUPT_EN	0x00010000
+
+/* "SC1200_VIP_STATUS" BIT DEFINITIONS */
+
+#define	SC1200_VIP_CURRENT_FIELD_ODD		0x01000000
+#define SC1200_VIP_BASE_NOT_UPDATED         0x00200000
+#define	SC1200_VIP_FIFO_OVERFLOW			0x00100000
+#define	SC1200_VIP_CLEAR_LINE_INT			0x00020000
+#define	SC1200_VIP_CLEAR_FIELD_INT			0x00010000
+#define	SC1200_VBI_DATA_CAPTURE_ACTIVE		0x00000200
+#define	SC1200_VIDEO_DATA_CAPTURE_ACTIVE	0x00000100
+
+/* "SC1200_VIP_CURRENT_LINE" BIT DEFINITIONS */
+
+#define SC1200_VIP_CURRENT_LINE_MASK	    0x000003FF
+
+/* "SC1200_VIP_LINE_TARGET" BIT DEFINITIONS */
+
+#define SC1200_VIP_LAST_LINE_MASK	        0x03FF0000
+
+/* "SC1200_VIP_PITCH" BIT DEFINITION */
+
+#define SC1200_VIP_PITCH_MASK               0x0000FFFC
+
+/* "SC1200_VBI_PITCH" BIT DEFINITION */
+
+#define SC1200_VBI_PITCH_MASK               0x0000FFFC
+
+/* SC1200 DIRECT VBI LINE ENABLE BIT DEFINITION */
+
+#define SC1200_DIRECT_VBI_LINE_ENABLE_MASK  0x00FFFFFF
+
+/* SC1200 CONFIGURATION BLOCK */
+
+#define SC1200_CB_BASE_ADDR                 0x9000
+#define SC1200_CB_WDTO                      0x0000
+#define SC1200_CB_WDCNFG                    0x0002
+#define SC1200_CB_WDSTS                     0x0004
+#define SC1200_CB_TMVALUE                   0x0008
+#define SC1200_CB_TMCNFG                    0x000D
+#define SC1200_CB_PMR                       0x0030
+#define SC1200_CB_MCR                       0x0034
+#define SC1200_CB_INTSEL                    0x0038
+#define SC1200_CB_PID                       0x003C
+#define SC1200_CB_REV                       0x003D
+
+/* SC1200 HIGH RESOLUTION TIMER CONFIGURATION REGISTER BITS */
+
+#define SC1200_TMCLKSEL_27MHZ               0x2
+
+/*---------------------------------*/
+/*  PHILIPS SAA7114 VIDEO DECODER  */
+/*---------------------------------*/
+
+#define SAA7114_CHIPADDR					0x42
+
+/* VIDEO DECODER REGISTER DEFINITIONS */
+
+#define SAA7114_ANALOG_INPUT_CTRL1			0x02
+#define SAA7114_LUMINANCE_CONTROL           0x09
+#define SAA7114_BRIGHTNESS					0x0A
+#define SAA7114_CONTRAST					0x0B
+#define SAA7114_SATURATION					0x0C
+#define SAA7114_HUE							0x0D
+#define SAA7114_STATUS						0x1F
+#define SAA7114_IPORT_CONTROL				0x86
+
+/* TASK A REGISTER DEFINITIONS */
+
+#define SAA7114_TASK_A_HORZ_OUTPUT_LO		0x9C
+#define SAA7114_TASK_A_HORZ_OUTPUT_HI		0x9D
+#define SAA7114_TASK_A_HSCALE_LUMA_LO		0xA8
+#define SAA7114_TASK_A_HSCALE_LUMA_HI		0xA9
+#define SAA7114_TASK_A_HSCALE_CHROMA_LO		0xAC
+#define SAA7114_TASK_A_HSCALE_CHROMA_HI		0xAD
+
+/* TASK B REGISTER DEFINITIONS */
+
+#define SAA7114_HORZ_OFFSET_LO				0xC4
+#define SAA7114_HORZ_OFFSET_HI				0xC5
+#define SAA7114_HORZ_INPUT_LO				0xC6
+#define SAA7114_HORZ_INPUT_HI				0xC7
+#define SAA7114_VERT_OFFSET_LO				0xC8
+#define SAA7114_VERT_OFFSET_HI				0xC9
+#define SAA7114_VERT_INPUT_LO				0xCA
+#define SAA7114_VERT_INPUT_HI				0xCB
+#define SAA7114_HORZ_OUTPUT_LO				0xCC
+#define SAA7114_HORZ_OUTPUT_HI				0xCD
+#define SAA7114_VERT_OUTPUT_LO				0xCE
+#define SAA7114_VERT_OUTPUT_HI				0xCF
+#define SAA7114_HORZ_PRESCALER				0xD0
+#define SAA7114_HORZ_ACL					0xD1
+#define SAA7114_HORZ_FIR_PREFILTER			0xD2
+#define SAA7114_FILTER_CONTRAST				0xD5
+#define SAA7114_FILTER_SATURATION			0xD6
+#define SAA7114_HSCALE_LUMA_LO				0xD8
+#define SAA7114_HSCALE_LUMA_HI				0xD9
+#define SAA7114_HSCALE_CHROMA_LO			0xDC
+#define SAA7114_HSCALE_CHROMA_HI			0xDD
+#define SAA7114_VSCALE_LUMA_LO				0xE0
+#define SAA7114_VSCALE_LUMA_HI				0xE1
+#define SAA7114_VSCALE_CHROMA_LO			0xE2
+#define SAA7114_VSCALE_CHROMA_HI			0xE3
+#define SAA7114_VSCALE_CONTROL				0xE4
+#define SAA7114_VSCALE_CHROMA_OFFS0			0xE8
+#define SAA7114_VSCALE_CHROMA_OFFS1			0xE9
+#define SAA7114_VSCALE_CHROMA_OFFS2			0xEA
+#define SAA7114_VSCALE_CHROMA_OFFS3			0xEB
+#define SAA7114_VSCALE_LUMINA_OFFS0			0xEC
+#define SAA7114_VSCALE_LUMINA_OFFS1			0xED
+#define SAA7114_VSCALE_LUMINA_OFFS2			0xEE
+#define SAA7114_VSCALE_LUMINA_OFFS3			0xEF
+
+
+/* Still need to determine PHO value (common phase offset) */
+#define SAA7114_VSCALE_PHO					0x00
+
+
+/*----------------------------------------------*/
+/*  SECOND GENERATION GRAPHICS UNIT (REDCLOUD)  */
+/*----------------------------------------------*/
+
+#define MGP_DST_OFFSET			0x0000		/* dst address				*/
+#define MGP_SRC_OFFSET			0x0004		/* src address				*/
+#define MGP_VEC_ERR				0x0004		/* vector diag/axial errors	*/
+#define MGP_STRIDE				0x0008		/* src and dst strides		*/
+#define MGP_WID_HEIGHT			0x000C		/* width and height of BLT	*/
+#define MGP_VEC_LEN				0x000C		/* vector length/init error */
+#define MGP_SRC_COLOR_FG		0x0010		/* src mono data fgcolor 	*/
+#define MGP_SRC_COLOR_BG		0x0014		/* src mono data bkcolor 	*/
+#define MGP_PAT_COLOR_0			0x0018		/* pattern color 0			*/
+#define MGP_PAT_COLOR_1			0x001C		/* pattern color 1			*/
+#define MGP_PAT_COLOR_2			0x0020		/* pattern color 2			*/
+#define MGP_PAT_COLOR_3			0x0024		/* pattern color 3			*/
+#define MGP_PAT_COLOR_4			0x0028		/* pattern color 4			*/
+#define MGP_PAT_COLOR_5			0x002C		/* pattern color 5			*/
+#define MGP_PAT_DATA_0			0x0030		/* pattern data 0			*/
+#define MGP_PAT_DATA_1			0x0034		/* pattern data 1			*/
+#define MGP_RASTER_MODE			0x0038		/* raster operation			*/
+#define MGP_VECTOR_MODE			0x003C		/* render vector			*/
+#define MGP_BLT_MODE			0x0040		/* render BLT				*/
+#define MGP_BLT_STATUS			0x0044		/* BLT status register		*/
+#define MGP_RESET				0x0044		/* reset register (write)	*/
+#define MGP_HST_SOURCE			0x0048		/* host src data (bitmap)	*/
+#define MGP_BASE_OFFSET			0x004C		/* base render offset		*/
+
+/* MGP_RASTER_MODE DEFINITIONS */
+
+#define MGP_RM_BPPFMT_332		    0x00000000	/* 8 BPP, 3:3:2				*/
+#define MGP_RM_BPPFMT_4444		    0x40000000	/* 16 BPP, 4:4:4:4			*/
+#define MGP_RM_BPPFMT_1555		    0x50000000	/* 16 BPP, 1:5:5:5			*/
+#define MGP_RM_BPPFMT_565		    0x60000000	/* 16 BPP, 5:6:5			*/
+#define MGP_RM_BPPFMT_8888		    0x80000000	/* 32 BPP, 8:8:8:8			*/
+#define MGP_RM_ALPHA_EN_MASK        0x00C00000  /* Alpha enable             */
+#define MGP_RM_ALPHA_TO_RGB         0x00400000  /* Alpha applies to RGB     */
+#define MGP_RM_ALPHA_TO_ALPHA       0x00800000  /* Alpha applies to alpha   */
+#define MGP_RM_ALPHA_OP_MASK        0x00300000  /* Alpha operation          */
+#define MGP_RM_ALPHA_TIMES_A        0x00000000  /* Alpha * A                */
+#define MGP_RM_BETA_TIMES_B         0x00100000  /* (1-alpha) * B            */
+#define MGP_RM_A_PLUS_BETA_B        0x00200000  /* A + (1-alpha) * B        */
+#define MGP_RM_ALPHA_A_PLUS_BETA_B  0x00300000  /* alpha * A + (1 - alpha)B */
+#define MGP_RM_ALPHA_SELECT         0x000E0000  /* Alpha Select             */
+#define MGP_RM_SELECT_ALPHA_A       0x00000000  /* Alpha from channel A     */
+#define MGP_RM_SELECT_ALPHA_B       0x00020000  /* Alpha from channel B     */
+#define MGP_RM_SELECT_ALPHA_R       0x00040000  /* Registered alpha         */
+#define MGP_RM_SELECT_ALPHA_1       0x00060000  /* Constant 1               */
+#define MGP_RM_SELECT_ALPHA_CHAN_A  0x00080000  /* RGB Values from A        */
+#define MGP_RM_SELECT_ALPHA_CHAN_B  0x000A0000  /* RGB Values from B        */
+#define MGP_RM_DEST_FROM_CHAN_A     0x00010000  /* Alpha channel select     */
+#define MGP_RM_PAT_FLAGS		    0x00000700  /* pattern related bits		*/
+#define MGP_RM_PAT_MONO			    0x00000100  /* monochrome pattern		*/
+#define MGP_RM_PAT_COLOR		    0x00000200  /* color pattern			*/
+#define MGP_RM_PAT_TRANS		    0x00000400	/* pattern transparency		*/
+#define MGP_RM_SRC_TRANS		    0x00000800	/* source transparency		*/
+
+/* MGP_VECTOR_MODE DEFINITIONS */
+
+#define MGP_VM_DST_REQ			0x00000008	/* dst data required		*/
+#define MGP_VM_THROTTLE			0x00000010  /* sync to VBLANK			*/
+
+/* MGP_BLT_MODE DEFINITIONS */
+
+#define MGP_BM_SRC_FB			0x00000001  /* src = frame buffer		*/
+#define MGP_BM_SRC_HOST			0x00000002  /* src = host register		*/
+#define MGP_BM_DST_REQ			0x00000004  /* dst data required		*/
+#define MGP_BM_SRC_MONO			0x00000040  /* monochrome source data   */
+#define MGP_BM_SRC_BP_MONO      0x00000080  /* Byte-packed monochrome   */
+#define MGP_BM_NEG_YDIR			0x00000100  /* negative Y direction		*/
+#define MGP_BM_NEG_XDIR			0x00000200  /* negative X direction		*/
+#define MGP_BM_THROTTLE			0x00000400  /* sync to VBLANK			*/
+
+/* MGP_BLT_STATUS DEFINITIONS */
+
+#define MGP_BS_BLT_BUSY			0x00000001  /* GP is not idle			*/
+#define MGP_BS_BLT_PENDING		0x00000004	/* second BLT is pending	*/
+#define MGP_BS_HALF_EMPTY		0x00000008  /* src FIFO half empty		*/
+
+/* ALPHA BLENDING MODES       */
+
+#define ALPHA_MODE_BLEND        0x00000000
+
+/*---------------------------------------------------*/
+/*  SECOND GENERATION DISPLAY CONTROLLER (REDCLOUD)  */
+/*---------------------------------------------------*/
+
+#define MDC_UNLOCK              0x00000000  /* Unlock register               */
+#define MDC_GENERAL_CFG         0x00000004  /* Config registers              */
+#define MDC_DISPLAY_CFG         0x00000008  
+#define MDC_GFX_SCL             0x0000000C  /* Graphics scaling              */
+
+#define MDC_FB_ST_OFFSET        0x00000010  /* Frame buffer start offset     */
+#define MDC_CB_ST_OFFSET        0x00000014  /* Compression start offset      */
+#define MDC_CURS_ST_OFFSET      0x00000018  /* Cursor buffer start offset    */
+#define MDC_ICON_ST_OFFSET      0x0000001C  /* Icon buffer start offset      */
+#define MDC_VID_Y_ST_OFFSET     0x00000020  /* Video Y Buffer start offset   */
+#define MDC_VID_U_ST_OFFSET     0x00000024  /* Video U Buffer start offset   */
+#define MDC_VID_V_ST_OFFSET     0x00000028  /* Video V Buffer start offset   */
+#define MDC_LINE_SIZE           0x00000030  /* Video, CB, and FB line sizes  */
+#define MDC_GFX_PITCH           0x00000034  /* FB and DB skip counts         */
+#define MDC_VID_YUV_PITCH       0x00000038  /* Y, U and V buffer skip counts */
+
+#define MDC_H_ACTIVE_TIMING     0x00000040  /* Horizontal timings            */
+#define MDC_H_BLANK_TIMING      0x00000044
+#define MDC_H_SYNC_TIMING       0x00000048
+#define MDC_V_ACTIVE_TIMING     0x00000050  /* Vertical Timings              */
+#define MDC_V_BLANK_TIMING      0x00000054
+#define MDC_V_SYNC_TIMING       0x00000058
+
+#define MDC_CURSOR_X            0x00000060  /* Cursor X position             */
+#define MDC_CURSOR_Y            0x00000064  /* Cursor Y Position             */
+#define MDC_ICON_X              0x00000068  /* Icon X Position               */
+#define MDC_LINE_CNT_STATUS     0x0000006C  /* Icon Y Position               */
+
+#define MDC_PAL_ADDRESS         0x00000070  /* Palette Address               */
+#define MDC_PAL_DATA            0x00000074  /* Palette Data                  */
+#define MDC_DFIFO_DIAG          0x00000078  /* Display FIFO diagnostic       */
+#define MDC_CFIFO_DIAG          0x0000007C  /* Compression FIFO diagnostic   */
+
+#define MDC_VID_DS_DELTA        0x00000080  /* Vertical Downscaling fraction */
+
+#define MDC_PHY_MEM_OFFSET      0x00000084  /* VG Base Address Register      */
+#define MDC_DV_CTL              0x00000088  /* Dirty-Valid Control Register  */
+#define MDC_DV_ACC              0x0000008C  /* Dirty-Valid RAM Access        */
+
+/* UNLOCK VALUE */
+
+#define MDC_UNLOCK_VALUE		0x00004758		/* used to unlock DC regs	*/
+
+/* VG MBUS DEVICE SMI MSR FIELDS */
+
+#define MDC_VG_BL_MASK            0x00000001
+#define MDC_MISC_MASK             0x00000002
+#define MDC_ISR0_MASK             0x00000004
+#define MDC_VGA_BL_MASK           0x00000008
+#define MDC_CRTCIO_MSK            0x00000010
+#define MDC_VG_BLANK_SMI          0x00000001
+#define MDC_MISC_SMI              0x00000002
+#define MDC_ISR0_SMI              0x00000004
+#define MDC_VGA_BLANK_SMI         0x00000008
+#define MDC_CRTCIO_SMI            0x00000010
+
+/* MDC_GENERAL_CFG BIT FIELDS */
+
+#define MDC_GCFG_DBUG             0x80000000
+#define MDC_GCFG_DBSL             0x40000000
+#define MDC_GCFG_CFRW             0x20000000
+#define MDC_GCFG_DIAG             0x10000000
+#define MDC_GCFG_GXRFS4           0x08000000
+#define MDC_GCFG_SGFR             0x04000000
+#define MDC_GCFG_SGRE             0x02000000
+#define MDC_GCFG_SIGE             0x01000000
+#define MDC_GCFG_YUVM             0x00100000
+#define MDC_GCFG_VDSE             0x00080000
+#define MDC_GCFG_VGAFT            0x00040000
+#define MDC_GCFG_FDTY             0x00020000
+#define MDC_GCFG_STFM             0x00010000
+#define MDC_GCFG_DFHPEL_MASK      0x0000F000
+#define MDC_GCFG_DFHPSL_MASK      0x00000F00
+#define MDC_GCFG_VGAE             0x00000080
+#define MDC_GCFG_DECE             0x00000040
+#define MDC_GCFG_CMPE             0x00000020
+#define MDC_GCFG_VIDE             0x00000008
+#define MDC_GCFG_ICNE             0x00000004
+#define MDC_GCFG_CURE             0x00000002
+#define MDC_GCFG_DFLE             0x00000001
+
+/* MDC_DISPLAY_CFG BIT FIELDS */
+
+#define MDC_DCFG_A20M             0x80000000
+#define MDC_DCFG_A18M             0x40000000
+#define MDC_DCFG_VISL             0x08000000
+#define MDC_DCFG_FRLK             0x04000000
+#define MDC_DCFG_PALB             0x02000000
+#define MDC_DCFG_PIX_PAN_MASK     0x00F00000
+#define MDC_DCFG_DCEN             0x00080000
+#define MDC_DCFG_16BPP_MODE_MASK  0x00000C00
+#define MDC_DCFG_16BPP            0x00000000        
+#define MDC_DCFG_15BPP            0x00000400
+#define MDC_DCFG_12BPP            0x00000800
+#define MDC_DCFG_DISP_MODE_MASK   0x00000300
+#define MDC_DCFG_DISP_MODE_8BPP   0x00000000
+#define MDC_DCFG_DISP_MODE_16BPP  0x00000100
+#define MDC_DCFG_DISP_MODE_24BPP  0x00000200
+#define MDC_DCFG_SCLE             0x00000080
+#define MDC_DCFG_TRUP             0x00000040
+#define MDC_DCFG_VIEN             0x00000020
+#define MDC_DCFG_VDEN             0x00000010
+#define MDC_DCFG_GDEN             0x00000008
+#define MDC_DCFG_VCKE             0x00000004
+#define MDC_DCFG_PCKE             0x00000002
+#define MDC_DCFG_TGEN             0x00000001
+
+/* MDC_LINE_CNT BIT FIELDS     */
+
+#define MDC_LNCNT_DNA             0x80000000
+#define MDC_LNCNT_VNA             0x40000000
+#define MDC_LNCNT_VSA             0x20000000
+#define MDC_LNCNT_VINT            0x10000000
+#define MDC_LNCNT_FLIP            0x08000000
+#define MDC_LNCNT_V_LINE_CNT      0x07FF0000
+#define MDC_LNCNT_VFLIP           0x00008000
+#define MDC_LNCNT_SIGC            0x00004000
+#define MDC_LNCNT_SS_LINE_CMP     0x000007FF
+
+/* MDC_FB_ST_OFFSET BIT FIELDS */
+
+#define MDC_FB_ST_OFFSET_MASK     0x0FFFFFFF
+
+/* MDC_CB_ST_OFFSET BIT FIELDS */
+
+#define MDC_CB_ST_OFFSET_MASK     0x0FFFFFFF
+
+/* MDC_CURS_ST_OFFSET BIT FIELDS */
+
+#define MDC_CURS_ST_OFFSET_MASK   0x0FFFFFFF
+
+/* MDC_ICON_ST_OFFSET BIT FIELDS */
+
+#define MDC_ICON_ST_OFFSET_MASK   0x0FFFFFFF
+
+/* MDC_VID_Y_ST_OFFSET BIT FIELDS */
+
+#define MDC_VID_Y_ST_OFFSET_MASK  0x0FFFFFFF
+
+/* MDC_VID_U_ST_OFFSET BIT FIELDS */
+
+#define MDC_VID_U_ST_OFFSET_MASK  0x0FFFFFFF
+
+/* MDC_VID_V_ST_OFFSET BIT FIELDS */
+
+#define MDC_VID_V_ST_OFFSET_MASK  0x0FFFFFFF
+
+/* MDC_LINE_SIZE BIT FIELDS */
+
+#define MDC_LINE_SIZE_VLS_MASK    0xFF000000
+#define MDC_LINE_SIZE_CBLS_MASK   0x007F0000
+#define MDC_LINE_SIZE_FBLS_MASK   0x000007FF
+
+/* MDC_GFX_PITCH BIT FIELDS */
+
+#define MDC_GFX_PITCH_CBP_MASK    0xFFFF0000
+#define MDC_GFX_PITCH_FBP_MASK    0x0000FFFF
+
+/* MDC_VID_YUV_PITCH BIT FIELDS */
+
+#define MDC_YUV_PITCH_UVP_MASK    0xFFFF0000
+#define MDC_YUV_PITCH_YBP_MASK    0x0000FFFF
+
+/* MDC_H_ACTIVE_TIMING BIT FIELDS */
+
+#define MDC_HAT_HT_MASK           0x0FF80000
+#define MDC_HAT_HA_MASK           0x00000FF8
+
+/* MDC_H_BLANK_TIMING BIT FIELDS */
+
+#define MDC_HBT_HBE_MASK          0x0FF80000
+#define MDC_HBT_HBS_MASK          0x00000FF8
+
+/* MDC_H_SYNC_TIMING BIT FIELDS */
+
+#define MDC_HST_HSE_MASK          0x0FF80000
+#define MDC_HST_HSS_MASK          0x00000FF8 
+
+/* MDC_V_ACTIVE_TIMING BIT FIELDS */
+
+#define MDC_VAT_VT_MASK           0x07FF0000
+#define MDC_VAT_VA_MASK           0x000007FF
+
+/* MDC_V_BLANK_TIMING BIT FIELDS */
+
+#define MDC_VBT_VBE_MASK          0x07FF0000
+#define MDC_VBT_VBS_MASK          0x000007FF
+
+/* MDC_V_SYNC_TIMING BIT FIELDS */
+
+#define MDC_VST_VSE_MASK          0x07FF0000
+#define MDC_VST_VSS_MASK          0x000007FF 
+
+/* MDC_DV_CTL BIT DEFINITIONS */
+
+#define MDC_DV_LINE_SIZE_MASK     0x00000C00
+#define MDC_DV_LINE_SIZE_1024     0x00000000
+#define MDC_DV_LINE_SIZE_2048     0x00000400
+#define MDC_DV_LINE_SIZE_4096     0x00000800
+#define MDC_DV_LINE_SIZE_8192     0x00000C00
+
+/* VGA DEFINITIONS */
+
+#define MDC_SEQUENCER_INDEX       0x03C4
+#define MDC_SEQUENCER_DATA        0x03C5
+#define MDC_SEQUENCER_RESET       0x00
+#define MDC_SEQUENCER_CLK_MODE    0x01
+
+#define MDC_RESET_VGA_DISP_ENABLE 0x03
+#define MDC_CLK_MODE_SCREEN_OFF   0x20
+
+
+/*---------------------------------------------------*/
+/*  REDCLOUD DISPLAY FILTER                          */
+/*---------------------------------------------------*/
+
+/* RCDF VIDEO REGISTER DEFINITIONS */
+
+#define RCDF_VIDEO_CONFIG 				    0x000
+#define RCDF_DISPLAY_CONFIG				    0x008
+#define RCDF_VIDEO_X_POS					0x010
+#define RCDF_VIDEO_Y_POS					0x018
+#define RCDF_VIDEO_SCALE					0x020
+#define RCDF_VIDEO_COLOR_KEY				0x028
+#define RCDF_VIDEO_COLOR_MASK				0x030
+#define RCDF_PALETTE_ADDRESS 				0x038
+#define RCDF_PALETTE_DATA	 				0x040
+#define RCDF_VID_MISC						0x050
+#define RCDF_VID_CLOCK_SELECT				0x058
+#define RCDF_VIDEO_DOWNSCALER_CONTROL       0x078 
+#define RCDF_VIDEO_DOWNSCALER_COEFFICIENTS  0x080  
+#define RCDF_VID_CRC						0x088
+#define RCDF_VID_CRC32						0x090
+#define RCDF_VID_ALPHA_CONTROL			    0x098
+#define RCDF_CURSOR_COLOR_KEY				0x0A0
+#define RCDF_CURSOR_COLOR_MASK			    0x0A8
+#define RCDF_CURSOR_COLOR_1				    0x0B0
+#define RCDF_CURSOR_COLOR_2				    0x0B8
+#define RCDF_ALPHA_XPOS_1					0x0C0
+#define RCDF_ALPHA_YPOS_1					0x0C8
+#define RCDF_ALPHA_COLOR_1				    0x0D0
+#define RCDF_ALPHA_CONTROL_1				0x0D8
+#define RCDF_ALPHA_XPOS_2					0x0E0
+#define RCDF_ALPHA_YPOS_2					0x0E8
+#define RCDF_ALPHA_COLOR_2				    0x0F0
+#define RCDF_ALPHA_CONTROL_2				0x0F8
+#define RCDF_ALPHA_XPOS_3					0x100
+#define RCDF_ALPHA_YPOS_3					0x108
+#define RCDF_ALPHA_COLOR_3				    0x110
+#define RCDF_ALPHA_CONTROL_3				0x118
+#define RCDF_VIDEO_REQUEST                  0x120
+#define RCDF_ALPHA_WATCH                    0x128
+#define RCDF_VIDEO_TEST_MODE                0x210
+#define RCDF_POWER_MANAGEMENT               0x410
+
+/* DISPLAY FILTER POWER MANAGEMENT DEFINITIONS */
+
+#define RCDF_PM_PANEL_POWER_ON              0x01000000
+
+/* DISPLAY FILTER MSRS */
+
+#define RCDF_MBD_MSR_DIAG_DF				0x2010
+#define RCDF_DIAG_32BIT_CRC					0x80000000
+
+/* "RCDF_VIDEO_CONFIG" BIT DEFINITIONS */
+
+#define RCDF_VCFG_VID_EN					0x00000001	
+#define RCDF_VCFG_VID_INP_FORMAT			0x0000000C	
+#define RCDF_VCFG_X_FILTER_EN				0x00000040	
+#define RCDF_VCFG_Y_FILTER_EN				0x00000080	
+#define RCDF_VCFG_LINE_SIZE_LOWER_MASK	    0x0000FF00	
+#define RCDF_VCFG_INIT_READ_MASK			0x01FF0000	
+#define RCDF_VCFG_LINE_SIZE_UPPER			0x08000000	
+#define RCDF_VCFG_4_2_0_MODE				0x10000000	
+#define RCDF_VCFG_UYVY_FORMAT				0x00000000
+#define RCDF_VCFG_Y2YU_FORMAT				0x00000004
+#define RCDF_VCFG_YUYV_FORMAT				0x00000008
+#define RCDF_VCFG_YVYU_FORMAT				0x0000000C
+
+/* "RCDF_DISPLAY_CONFIG" BIT DEFINITIONS */
+
+#define RCDF_DCFG_DIS_EN				    0x00000001	
+#define RCDF_DCFG_HSYNC_EN				    0x00000002	
+#define RCDF_DCFG_VSYNC_EN				    0x00000004	
+#define RCDF_DCFG_DAC_BL_EN				    0x00000008	
+#define RCDF_DCFG_FP_PWR_EN				    0x00000040
+#define RCDF_DCFG_FP_DATA_EN				0x00000080	
+#define RCDF_DCFG_CRT_HSYNC_POL 			0x00000100	
+#define RCDF_DCFG_CRT_VSYNC_POL 			0x00000200		
+#define RCDF_DCFG_CRT_SYNC_SKW_MASK		    0x0001C000
+#define RCDF_DCFG_CRT_SYNC_SKW_INIT		    0x00010000
+#define RCDF_DCFG_PWR_SEQ_DLY_MASK		    0x000E0000
+#define RCDF_DCFG_PWR_SEQ_DLY_INIT		    0x00080000
+#define RCDF_DCFG_VG_CK					    0x00100000
+#define RCDF_DCFG_GV_PAL_BYP				0x00200000
+#define RCDF_DAC_VREF                       0x04000000
+#define RCDF_FP_ON_STATUS                   0x08000000
+
+/* "RCDF_VID_MISC" BIT DEFINITIONS */
+
+#define RCDF_GAMMA_BYPASS_BOTH              0x00000001
+#define RCDF_DAC_POWER_DOWN                 0x00000400
+#define RCDF_ANALOG_POWER_DOWN              0x00000800
+
+/* "RCDF_VIDEO_DOWNSCALER_CONTROL" BIT DEFINITIONS */
+
+#define RCDF_VIDEO_DOWNSCALE_ENABLE         0x00000001
+#define RCDF_VIDEO_DOWNSCALE_FACTOR_POS     1
+#define RCDF_VIDEO_DOWNSCALE_FACTOR_MASK    0x0000001E
+#define RCDF_VIDEO_DOWNSCALE_TYPE_A         0x00000000
+#define RCDF_VIDEO_DOWNSCALE_TYPE_B         0x00000040
+#define RCDF_VIDEO_DOWNSCALE_TYPE_MASK      0x00000040
+
+/* "RCDF_VIDEO_DOWNSCALER_COEFFICIENTS" BIT DEFINITIONS */
+
+#define RCDF_VIDEO_DOWNSCALER_COEF1_POS     0
+#define RCDF_VIDEO_DOWNSCALER_COEF2_POS     8
+#define RCDF_VIDEO_DOWNSCALER_COEF3_POS     16
+#define RCDF_VIDEO_DOWNSCALER_COEF4_POS     24
+#define RCDF_VIDEO_DOWNSCALER_COEF_MASK     0xF
+
+/* VIDEO DE-INTERLACING AND ALPHA CONTROL */
+
+#define RCDF_NO_CK_OUTSIDE_ALPHA            0x00000100
+#define RCDF_CSC_VIDEO_YUV_TO_RGB           0x00000400
+#define RCDF_VIDEO_INPUT_IS_RGB             0x00002000
+#define RCDF_ALPHA1_PRIORITY_POS			16
+#define RCDF_ALPHA1_PRIORITY_MASK			0x00030000
+#define RCDF_ALPHA2_PRIORITY_POS			18
+#define RCDF_ALPHA2_PRIORITY_MASK			0x000C0000
+#define RCDF_ALPHA3_PRIORITY_POS			20
+#define RCDF_ALPHA3_PRIORITY_MASK			0x00300000
+
+/* VIDEO CURSOR COLOR KEY DEFINITIONS */
+
+#define RCDF_CURSOR_COLOR_KEY_ENABLE      0x20000000
+#define RCDF_CURSOR_COLOR_KEY_OFFSET_POS  24
+#define RCDF_CURSOR_COLOR_BITS            23
+#define RCDF_COLOR_MASK                   0x00FFFFFF /* 24 significant bits */
+
+/* ALPHA COLOR BIT DEFINITION (REGISTERS 0x68, 0x78, AND 0x88) */
+
+#define RCDF_ALPHA_COLOR_ENABLE           0x01000000
+
+/* ALPHA CONTROL BIT DEFINITIONS (REGISTERS 0x6C, 0x7C, AND 0x8C) */
+
+#define RCDF_ACTRL_WIN_ENABLE				0x00010000
+#define RCDF_ACTRL_LOAD_ALPHA				0x00020000
+
+/* VIDEO REQUEST DEFINITIONS (REGISTER 0x90) */
+
+#define RCDF_VIDEO_Y_REQUEST_POS          0
+#define RCDF_VIDEO_X_REQUEST_POS          16
+#define RCDF_VIDEO_REQUEST_MASK           0x000007FF
+
+/* GEODELINK DEVICE MSR REGISTER SUMMARY */
+
+#define MBD_MSR_CAP         0x2000   /* Device Capabilities                   */
+#define MBD_MSR_CONFIG      0x2001   /* Device Master Configuration Register  */
+#define MBD_MSR_SMI         0x2002   /* MBus Device SMI Register              */
+#define MBD_MSR_ERROR       0x2003   /* MBus Device Error                     */
+#define MBD_MSR_PM          0x2004   /* MBus Device Power Management Register */
+#define MBD_MSR_DIAG        0x2005   /* Mbus Device Diagnostic Register       */
+
+/* DISPLAY FILTER MBD_MSR_DIAG DEFINITIONS */
+
+#define RCDF_MBD_DIAG_SEL0        0x00007FFF /* Lower 32-bits of Diag Bus Select     */
+#define RCDF_MBD_DIAG_EN0         0x00008000 /* Enable for lower 32-bits of diag bus */
+#define RCDF_MBD_DIAG_SEL1        0x7FFF0000 /* Upper 32-bits of Diag Bus Select     */
+#define RCDF_MBD_DIAG_EN1         0x80000000 /* Enable for upper 32-bits of diag bus */
+
+/* DISPLAY FILTER MBD_MSR_CONFIG DEFINITIONS */
+
+#define RCDF_CONFIG_FMT_MASK      0x00000038 /* Output Format */
+#define RCDF_CONFIG_FMT_CRT       0x00000000
+#define RCDF_CONFIG_FMT_FP        0x00000008 
+
+/* MCP MSR DEFINITIONS */
+
+#define MCP_CLKOFF                0x0010
+#define MCP_CLKACTIVE             0x0011
+#define MCP_CLKDISABLE            0x0012
+#define MCP_CLK4ACK               0x0013
+#define MCP_SYS_RSTPLL            0x0014
+#define MCP_DOTPLL                0x0015
+#define MCP_DBGCLKCTL             0x0016
+#define MCP_RC_REVID              0x0017
+#define MCP_SETM0CTL              0x0040
+#define MCP_SETN0CTL              0x0048
+#define MCP_CMPVAL0               0x0050
+#define MCP_CMPMASK0              0x0051
+#define MCP_REGA                  0x0058
+#define MCP_REGB                  0x0059
+#define MCP_REGAMASK              0x005A
+#define MCP_REGAVAL               0x005B
+#define MCP_REGBMASK              0x005C
+#define MCP_REGBVAL               0x005D
+#define MCP_FIFOCTL               0x005E
+#define MCP_DIAGCTL               0x005F
+#define MCP_H0CTL                 0x0060
+#define MCP_XSTATE                0x0066
+#define MCP_YSTATE                0x0067
+#define MCP_ACTION0               0x0068
+
+/* MCP_SYS_RSTPLL DEFINITIONS */
+
+#define MCP_DOTPOSTDIV3           0x00000008
+#define MCP_DOTPREMULT2           0x00000004
+#define MCP_DOTPREDIV2            0x00000002
+
+/* MCP MBD_MSR_DIAG DEFINITIONS */
+
+#define MCP_MBD_DIAG_SEL0         0x00000007
+#define MCP_MBD_DIAG_EN0          0x00008000
+#define MCP_MBD_DIAG_SEL1         0x00070000
+#define MCP_MBD_DIAG_EN1          0x80000000
+
+/* MCP_DOTPLL DEFINITIONS */
+
+#define MCP_DOTPLL_P              0x00000003
+#define MCP_DOTPLL_N              0x000001FC
+#define MCP_DOTPLL_M              0x00001E00
+#define MCP_DOTPLL_LOCK           0x02000000
+#define MCP_DOTPLL_BYPASS         0x00008000
+
+
+/*---------------------------------------------------*/
+/*  THIRD GENERATION DISPLAY CONTROLLER (CASTLE)     */
+/*---------------------------------------------------*/
+
+#define DC3_UNLOCK              0x00000000  /* Unlock register               */
+#define DC3_GENERAL_CFG         0x00000004  /* Config registers              */
+#define DC3_DISPLAY_CFG         0x00000008  
+
+#define DC3_FB_ST_OFFSET        0x00000010  /* Frame buffer start offset     */
+#define DC3_CB_ST_OFFSET        0x00000014  /* Compression start offset      */
+#define DC3_CURS_ST_OFFSET      0x00000018  /* Cursor buffer start offset    */
+#define DC3_VID_Y_ST_OFFSET     0x00000020  /* Video Y Buffer start offset   */
+#define DC3_VID_U_ST_OFFSET     0x00000024  /* Video U Buffer start offset   */
+#define DC3_VID_V_ST_OFFSET     0x00000028  /* Video V Buffer start offset   */
+#define DC3_LINE_SIZE           0x00000030  /* Video, CB, and FB line sizes  */
+#define DC3_GFX_PITCH           0x00000034  /* FB and DB skip counts         */
+#define DC3_VID_YUV_PITCH       0x00000038  /* Y, U and V buffer skip counts */
+
+#define DC3_H_ACTIVE_TIMING     0x00000040  /* Horizontal timings            */
+#define DC3_H_BLANK_TIMING      0x00000044
+#define DC3_H_SYNC_TIMING       0x00000048
+#define DC3_V_ACTIVE_TIMING     0x00000050  /* Vertical Timings              */
+#define DC3_V_BLANK_TIMING      0x00000054
+#define DC3_V_SYNC_TIMING       0x00000058
+
+#define DC3_CURSOR_X            0x00000060  /* Cursor X position             */
+#define DC3_CURSOR_Y            0x00000064  /* Cursor Y Position             */
+#define DC3_LINE_CNT_STATUS     0x0000006C  /* Icon Y Position               */
+
+#define DC3_PAL_ADDRESS         0x00000070  /* Palette Address               */
+#define DC3_PAL_DATA            0x00000074  /* Palette Data                  */
+#define DC3_DFIFO_DIAG          0x00000078  /* Display FIFO diagnostic       */
+#define DC3_CFIFO_DIAG          0x0000007C  /* Compression FIFO diagnostic   */
+
+#define DC3_VID_DS_DELTA        0x00000080  /* Vertical Downscaling fraction */
+
+#define DC3_PHY_MEM_OFFSET      0x00000084  /* VG Base Address Register      */
+#define DC3_DV_CTL              0x00000088  /* Dirty-Valid Control Register  */
+#define DC3_DV_ACC              0x0000008C  /* Dirty-Valid RAM Access        */
+
+#define DC3_COLOR_KEY           0x000000B8  /* Graphics color key            */
+#define DC3_COLOR_MASK          0x000000BC  /* Graphics color key mask       */
+
+/* UNLOCK VALUE */
+
+#define DC3_UNLOCK_VALUE		0x00004758		/* used to unlock DC regs	*/
+
+/* VG MBUS DEVICE SMI MSR FIELDS */
+
+#define DC3_VG_BL_MASK            0x00000001
+#define DC3_MISC_MASK             0x00000002
+#define DC3_ISR0_MASK             0x00000004
+#define DC3_VGA_BL_MASK           0x00000008
+#define DC3_CRTCIO_MSK            0x00000010
+#define DC3_VG_BLANK_SMI          0x00000001
+#define DC3_MISC_SMI              0x00000002
+#define DC3_ISR0_SMI              0x00000004
+#define DC3_VGA_BLANK_SMI         0x00000008
+#define DC3_CRTCIO_SMI            0x00000010
+
+/* DC3_GENERAL_CFG BIT FIELDS */
+
+#define DC3_GCFG_DBUG             0x80000000
+#define DC3_GCFG_DBSL             0x40000000
+#define DC3_GCFG_CFRW             0x20000000
+#define DC3_GCFG_DIAG             0x10000000
+#define DC3_GCFG_GXRFS4           0x08000000
+#define DC3_GCFG_SGFR             0x04000000
+#define DC3_GCFG_SGRE             0x02000000
+#define DC3_GCFG_SIGE             0x01000000
+#define DC3_GCFG_YUVM             0x00100000
+#define DC3_GCFG_VDSE             0x00080000
+#define DC3_GCFG_VGAFT            0x00040000
+#define DC3_GCFG_FDTY             0x00020000
+#define DC3_GCFG_STFM             0x00010000
+#define DC3_GCFG_DFHPEL_MASK      0x0000F000
+#define DC3_GCFG_DFHPSL_MASK      0x00000F00
+#define DC3_GCFG_VGAE             0x00000080
+#define DC3_GCFG_DECE             0x00000040
+#define DC3_GCFG_CMPE             0x00000020
+#define DC3_GCFG_VIDE             0x00000008
+#define DC3_GCFG_ICNE             0x00000004
+#define DC3_GCFG_CURE             0x00000002
+#define DC3_GCFG_DFLE             0x00000001
+
+/* DC3_DISPLAY_CFG BIT FIELDS */
+
+#define DC3_DCFG_A20M             0x80000000
+#define DC3_DCFG_A18M             0x40000000
+#define DC3_DCFG_VISL             0x08000000
+#define DC3_DCFG_FRLK             0x04000000
+#define DC3_DCFG_PALB             0x02000000
+#define DC3_DCFG_PIX_PAN_MASK     0x00F00000
+#define DC3_DCFG_DCEN             0x00080000
+#define DC3_DCFG_16BPP_MODE_MASK  0x00000C00
+#define DC3_DCFG_16BPP            0x00000000        
+#define DC3_DCFG_15BPP            0x00000400
+#define DC3_DCFG_12BPP            0x00000800
+#define DC3_DCFG_DISP_MODE_MASK   0x00000300
+#define DC3_DCFG_DISP_MODE_8BPP   0x00000000
+#define DC3_DCFG_DISP_MODE_16BPP  0x00000100
+#define DC3_DCFG_DISP_MODE_24BPP  0x00000200
+#define DC3_DCFG_SCLE             0x00000080
+#define DC3_DCFG_TRUP             0x00000040
+#define DC3_DCFG_VIEN             0x00000020
+#define DC3_DCFG_VDEN             0x00000010
+#define DC3_DCFG_GDEN             0x00000008
+#define DC3_DCFG_VCKE             0x00000004
+#define DC3_DCFG_PCKE             0x00000002
+#define DC3_DCFG_TGEN             0x00000001
+
+/* DC3_LINE_CNT BIT FIELDS     */
+
+#define DC3_LNCNT_DNA             0x80000000
+#define DC3_LNCNT_VNA             0x40000000
+#define DC3_LNCNT_VSA             0x20000000
+#define DC3_LNCNT_VINT            0x10000000
+#define DC3_LNCNT_FLIP            0x08000000
+#define DC3_LNCNT_V_LINE_CNT      0x07FF0000
+#define DC3_LNCNT_VFLIP           0x00008000
+#define DC3_LNCNT_SIGC            0x00004000
+#define DC3_LNCNT_SS_LINE_CMP     0x000007FF
+
+/* DC3_FB_ST_OFFSET BIT FIELDS */
+
+#define DC3_FB_ST_OFFSET_MASK     0x0FFFFFFF
+
+/* DC3_CB_ST_OFFSET BIT FIELDS */
+
+#define DC3_CB_ST_OFFSET_MASK     0x0FFFFFFF
+
+/* DC3_CURS_ST_OFFSET BIT FIELDS */
+
+#define DC3_CURS_ST_OFFSET_MASK   0x0FFFFFFF
+
+/* DC3_ICON_ST_OFFSET BIT FIELDS */
+
+#define DC3_ICON_ST_OFFSET_MASK   0x0FFFFFFF
+
+/* DC3_VID_Y_ST_OFFSET BIT FIELDS */
+
+#define DC3_VID_Y_ST_OFFSET_MASK  0x0FFFFFFF
+
+/* DC3_VID_U_ST_OFFSET BIT FIELDS */
+
+#define DC3_VID_U_ST_OFFSET_MASK  0x0FFFFFFF
+
+/* DC3_VID_V_ST_OFFSET BIT FIELDS */
+
+#define DC3_VID_V_ST_OFFSET_MASK  0x0FFFFFFF
+
+/* DC3_LINE_SIZE BIT FIELDS */
+
+#define DC3_LINE_SIZE_VLS_MASK    0x3FF00000
+#define DC3_LINE_SIZE_CBLS_MASK   0x0007F000
+#define DC3_LINE_SIZE_FBLS_MASK   0x000003FF
+#define DC3_LINE_SIZE_CB_SHIFT    12
+#define DC3_LINE_SIZE_VB_SHIFT    20
+
+/* DC3_GFX_PITCH BIT FIELDS */
+
+#define DC3_GFX_PITCH_CBP_MASK    0xFFFF0000
+#define DC3_GFX_PITCH_FBP_MASK    0x0000FFFF
+
+/* DC3_VID_YUV_PITCH BIT FIELDS */
+
+#define DC3_YUV_PITCH_UVP_MASK    0xFFFF0000
+#define DC3_YUV_PITCH_YBP_MASK    0x0000FFFF
+
+/* DC3_H_ACTIVE_TIMING BIT FIELDS */
+
+#define DC3_HAT_HT_MASK           0x0FF80000
+#define DC3_HAT_HA_MASK           0x00000FF8
+
+/* DC3_H_BLANK_TIMING BIT FIELDS */
+
+#define DC3_HBT_HBE_MASK          0x0FF80000
+#define DC3_HBT_HBS_MASK          0x00000FF8
+
+/* DC3_H_SYNC_TIMING BIT FIELDS */
+
+#define DC3_HST_HSE_MASK          0x0FF80000
+#define DC3_HST_HSS_MASK          0x00000FF8 
+
+/* DC3_V_ACTIVE_TIMING BIT FIELDS */
+
+#define DC3_VAT_VT_MASK           0x07FF0000
+#define DC3_VAT_VA_MASK           0x000007FF
+
+/* DC3_V_BLANK_TIMING BIT FIELDS */
+
+#define DC3_VBT_VBE_MASK          0x07FF0000
+#define DC3_VBT_VBS_MASK          0x000007FF
+
+/* DC3_V_SYNC_TIMING BIT FIELDS */
+
+#define DC3_VST_VSE_MASK          0x07FF0000
+#define DC3_VST_VSS_MASK          0x000007FF 
+
+/* DC3_DV_CTL BIT DEFINITIONS */
+
+#define DC3_DV_LINE_SIZE_MASK     0x00000C00
+#define DC3_DV_LINE_SIZE_1024     0x00000000
+#define DC3_DV_LINE_SIZE_2048     0x00000400
+#define DC3_DV_LINE_SIZE_4096     0x00000800
+#define DC3_DV_LINE_SIZE_8192     0x00000C00
+
+#define DC3_CLR_KEY_DATA_MASK     0x00FFFFFF
+#define DC3_CLR_KEY_ENABLE        0x01000000
+#define DC3_CLR_KEY_INVERT        0x02000000
+
+/* VGA DEFINITIONS */
+
+#define DC3_SEQUENCER_INDEX       0x03C4
+#define DC3_SEQUENCER_DATA        0x03C5
+#define DC3_SEQUENCER_RESET       0x00
+#define DC3_SEQUENCER_CLK_MODE    0x01
+
+#define DC3_RESET_VGA_DISP_ENABLE 0x03
+#define DC3_CLK_MODE_SCREEN_OFF   0x20
+
+/*---------------------------------------------------*/
+/*  CASTLE DISPLAY FILTER                          */
+/*---------------------------------------------------*/
+
+/* CASTLE VIDEO REGISTER DEFINITIONS */
+
+#define CASTLE_VIDEO_CONFIG 				    0x000
+#define CASTLE_DISPLAY_CONFIG				    0x008
+#define CASTLE_VIDEO_X_POS						0x010
+#define CASTLE_VIDEO_Y_POS						0x018
+#define CASTLE_VIDEO_COLOR_KEY					0x028
+#define CASTLE_VIDEO_COLOR_MASK					0x030
+#define CASTLE_PALETTE_ADDRESS 					0x038
+#define CASTLE_PALETTE_DATA	 					0x040
+#define CASTLE_VID_MISC							0x050
+#define CASTLE_VID_CLOCK_SELECT					0x058
+#define CASTLE_VIDEO_YSCALE                     0x060
+#define CASTLE_VIDEO_XSCALE                     0x068
+#define CASTLE_VIDEO_DOWNSCALER_CONTROL			0x078 
+#define CASTLE_VID_CRC							0x088
+#define CASTLE_VID_CRC32						0x090
+#define CASTLE_VID_ALPHA_CONTROL			    0x098
+#define CASTLE_CURSOR_COLOR_KEY					0x0A0
+#define CASTLE_CURSOR_COLOR_MASK			    0x0A8
+#define CASTLE_CURSOR_COLOR_1				    0x0B0
+#define CASTLE_CURSOR_COLOR_2				    0x0B8
+#define CASTLE_ALPHA_XPOS_1						0x0C0
+#define CASTLE_ALPHA_YPOS_1						0x0C8
+#define CASTLE_ALPHA_COLOR_1				    0x0D0
+#define CASTLE_ALPHA_CONTROL_1					0x0D8
+#define CASTLE_ALPHA_XPOS_2						0x0E0
+#define CASTLE_ALPHA_YPOS_2						0x0E8
+#define CASTLE_ALPHA_COLOR_2				    0x0F0
+#define CASTLE_ALPHA_CONTROL_2					0x0F8
+#define CASTLE_ALPHA_XPOS_3						0x100
+#define CASTLE_ALPHA_YPOS_3						0x108
+#define CASTLE_ALPHA_COLOR_3				    0x110
+#define CASTLE_ALPHA_CONTROL_3					0x118
+#define CASTLE_VIDEO_REQUEST					0x120
+#define CASTLE_ALPHA_WATCH						0x128
+#define CASTLE_VIDEO_TEST_MODE					0x210
+#define CASTLE_POWER_MANAGEMENT					0x410
+
+/* DISPLAY FILTER POWER MANAGEMENT DEFINITIONS */
+
+#define CASTLE_PM_PANEL_POWER_ON				0x01000000
+
+/* DISPLAY FILTER MSRS */
+
+#define CASTLE_MBD_MSR_DIAG_DF					0x2010
+#define CASTLE_DIAG_32BIT_CRC					0x80000000
+
+/* "CASTLE_VIDEO_CONFIG" BIT DEFINITIONS */
+
+#define CASTLE_VCFG_VID_EN						0x00000001	
+#define CASTLE_VCFG_VID_INP_FORMAT				0x0000000C
+#define CASTLE_VCFG_SCALER_BYPASS               0x00000020	
+#define CASTLE_VCFG_X_FILTER_EN					0x00000040	
+#define CASTLE_VCFG_Y_FILTER_EN					0x00000080	
+#define CASTLE_VCFG_LINE_SIZE_LOWER_MASK	    0x0000FF00	
+#define CASTLE_VCFG_INIT_READ_MASK				0x01FF0000	
+#define CASTLE_VCFG_LINE_SIZE_UPPER				0x08000000	
+#define CASTLE_VCFG_4_2_0_MODE					0x10000000	
+#define CASTLE_VCFG_UYVY_FORMAT					0x00000000
+#define CASTLE_VCFG_Y2YU_FORMAT					0x00000004
+#define CASTLE_VCFG_YUYV_FORMAT					0x00000008
+#define CASTLE_VCFG_YVYU_FORMAT					0x0000000C
+
+/* "CASTLE_DISPLAY_CONFIG" BIT DEFINITIONS */
+
+#define CASTLE_DCFG_DIS_EN						0x00000001	
+#define CASTLE_DCFG_HSYNC_EN				    0x00000002	
+#define CASTLE_DCFG_VSYNC_EN				    0x00000004	
+#define CASTLE_DCFG_DAC_BL_EN				    0x00000008	
+#define CASTLE_DCFG_FP_PWR_EN				    0x00000040
+#define CASTLE_DCFG_FP_DATA_EN					0x00000080	
+#define CASTLE_DCFG_CRT_HSYNC_POL 				0x00000100	
+#define CASTLE_DCFG_CRT_VSYNC_POL 				0x00000200		
+#define CASTLE_DCFG_CRT_SYNC_SKW_MASK		    0x0001C000
+#define CASTLE_DCFG_CRT_SYNC_SKW_INIT		    0x00010000
+#define CASTLE_DCFG_PWR_SEQ_DLY_MASK		    0x000E0000
+#define CASTLE_DCFG_PWR_SEQ_DLY_INIT		    0x00080000
+#define CASTLE_DCFG_VG_CK					    0x00100000
+#define CASTLE_DCFG_GV_PAL_BYP					0x00200000
+#define CASTLE_DAC_VREF							0x04000000
+#define CASTLE_FP_ON_STATUS						0x08000000
+
+/* "CASTLE_VID_MISC" BIT DEFINITIONS */
+
+#define CASTLE_GAMMA_BYPASS_BOTH				0x00000001
+#define CASTLE_DAC_POWER_DOWN					0x00000400
+#define CASTLE_ANALOG_POWER_DOWN				0x00000800
+
+/* "CASTLE_VIDEO_DOWNSCALER_CONTROL" BIT DEFINITIONS */
+
+#define CASTLE_VIDEO_DOWNSCALE_ENABLE			0x00000001
+#define CASTLE_VIDEO_DOWNSCALE_FACTOR_POS		1
+#define CASTLE_VIDEO_DOWNSCALE_FACTOR_MASK		0x0000001E
+#define CASTLE_VIDEO_DOWNSCALE_TYPE_A			0x00000000
+#define CASTLE_VIDEO_DOWNSCALE_TYPE_B			0x00000040
+#define CASTLE_VIDEO_DOWNSCALE_TYPE_MASK		0x00000040
+
+/* "CASTLE_VIDEO_DOWNSCALER_COEFFICIENTS" BIT DEFINITIONS */
+
+#define CASTLE_VIDEO_DOWNSCALER_COEF1_POS		0
+#define CASTLE_VIDEO_DOWNSCALER_COEF2_POS		8
+#define CASTLE_VIDEO_DOWNSCALER_COEF3_POS		16
+#define CASTLE_VIDEO_DOWNSCALER_COEF4_POS		24
+#define CASTLE_VIDEO_DOWNSCALER_COEF_MASK		0xF
+
+/* VIDEO DE-INTERLACING AND ALPHA CONTROL */
+
+#define CASTLE_NO_CK_OUTSIDE_ALPHA				0x00000100
+#define CASTLE_CSC_VIDEO_YUV_TO_RGB				0x00000400
+#define CASTLE_VIDEO_INPUT_IS_RGB				0x00002000
+#define CASTLE_ALPHA1_PRIORITY_POS				16
+#define CASTLE_ALPHA1_PRIORITY_MASK				0x00030000
+#define CASTLE_ALPHA2_PRIORITY_POS				18
+#define CASTLE_ALPHA2_PRIORITY_MASK				0x000C0000
+#define CASTLE_ALPHA3_PRIORITY_POS				20
+#define CASTLE_ALPHA3_PRIORITY_MASK				0x00300000
+
+/* VIDEO CURSOR COLOR KEY DEFINITIONS */
+
+#define CASTLE_CURSOR_COLOR_KEY_ENABLE			0x20000000
+#define CASTLE_CURSOR_COLOR_KEY_OFFSET_POS		24
+#define CASTLE_CURSOR_COLOR_BITS				23
+#define CASTLE_COLOR_MASK						0x00FFFFFF /* 24 significant bits */
+
+/* ALPHA COLOR BIT DEFINITION (REGISTERS 0x68, 0x78, AND 0x88) */
+
+#define CASTLE_ALPHA_COLOR_ENABLE				0x01000000
+
+/* ALPHA CONTROL BIT DEFINITIONS (REGISTERS 0x6C, 0x7C, AND 0x8C) */
+
+#define CASTLE_ACTRL_WIN_ENABLE					0x00010000
+#define CASTLE_ACTRL_LOAD_ALPHA					0x00020000
+
+/* VIDEO REQUEST DEFINITIONS (REGISTER 0x90) */
+
+#define CASTLE_VIDEO_Y_REQUEST_POS				0
+#define CASTLE_VIDEO_X_REQUEST_POS				16
+#define CASTLE_VIDEO_REQUEST_MASK				0x000007FF
+
+/* END OF FILE */
+
diff -uNr linux-2.4.31/drivers/video/nsc/gfx/gfx_rndr.c linux-fb/drivers/video/nsc/gfx/gfx_rndr.c
--- linux-2.4.31/drivers/video/nsc/gfx/gfx_rndr.c	1970-01-01 01:00:00.000000000 +0100
+++ linux-fb/drivers/video/nsc/gfx/gfx_rndr.c	2005-10-13 17:50:36.000000000 +0200
@@ -0,0 +1,630 @@
+/*
+ * <LIC_AMD_STD>
+ * Copyright (c) 2004 Advanced Micro Devices, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * 
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING
+ * </LIC_AMD_STD>
+ * <CTL_AMD_STD>
+ * </CTL_AMD_STD>
+ * <DOC_AMD_STD>
+ * This file contains routines to program the 2D acceleration hardware:
+ * 
+ *    gfx_set_bpp
+ *    gfx_set_solid_pattern
+ *    gfx_set_mono_pattern
+ *    gfx_set_color_pattern
+ *    gfx_load_color_pattern_line
+ *    gfx_set_solid_source  
+ *    gfx_set_mono_source
+ *    gfx_set_raster_operation
+ *    gfx_pattern_fill
+ *    gfx_color_pattern_fill
+ *    gfx_screen_to_screen_blt
+ *    gfx_screen_to_screen_xblt
+ *    gfx_color_bitmap_to_screen_blt
+ *    gfx_color_bitmap_to_screen_xblt
+ *    gfx_mono_bitmap_to_screen_blt
+ *    gfx_bresenham_line 
+ *    gfx_wait_until_idle   
+ * </DOC_AMD_STD>
+ */
+
+
+/* STATIC VARIABLES */
+
+unsigned short GFXbpp = 16;
+unsigned short GFXbb0Base = 0x400;
+unsigned short GFXbb1Base = 0x930;
+unsigned short GFXbufferWidthPixels = 400;
+
+unsigned short GFXpatternFlags = 0;
+unsigned short GFXsourceFlags = 0;
+unsigned long GFXsavedColor = 0;
+unsigned short GFXsavedRop = 0;
+unsigned short GFXusesDstData = 0;
+
+/* INCLUDE SUPPORT FOR FIRST GENERATION, IF SPECIFIED. */
+
+#if GFX_2DACCEL_GU1
+#include "rndr_gu1.c"
+#endif
+
+/* INCLUDE SUPPORT FOR SECOND GENERATION, IF SPECIFIED. */
+
+#if GFX_2DACCEL_GU2
+#include "rndr_gu2.c"
+#endif
+
+/* WRAPPERS IF DYNAMIC SELECTION */
+/* Extra layer to call either first or second generation routines. */
+
+#if GFX_2DACCEL_DYNAMIC
+
+/*---------------------------------------------------------------------------
+ * gfx_reset_pitch (PRIVATE ROUTINE - NOT PART OF API)
+ *---------------------------------------------------------------------------
+ */
+void gfx_reset_pitch(unsigned short pitch)
+{
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_reset_pitch(pitch);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_bpp
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_bpp(unsigned short bpp)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_set_bpp(bpp);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_set_bpp(bpp);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_solid_source
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_solid_source(unsigned long color)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_set_solid_source(color);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_set_solid_source(color);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_mono_source
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_mono_source(unsigned long bgcolor, unsigned long fgcolor,
+	unsigned short transparent)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_set_mono_source(bgcolor, fgcolor, transparent);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_set_mono_source(bgcolor, fgcolor, transparent);
+#endif
+}
+
+void gfx_set_pattern_flags(unsigned short flags)
+{
+	GFXpatternFlags |= flags;
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_solid_pattern
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_solid_pattern(unsigned long color)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_set_solid_pattern(color);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_set_solid_pattern(color);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_mono_pattern
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_mono_pattern(unsigned long bgcolor, unsigned long fgcolor, 
+	unsigned long data0, unsigned long data1, unsigned char transparent)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_set_mono_pattern(bgcolor, fgcolor, data0, data1, transparent);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_set_mono_pattern(bgcolor, fgcolor, data0, data1, transparent);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_color_pattern
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_color_pattern(unsigned long bgcolor, unsigned long fgcolor, 
+	unsigned long data0, unsigned long data1, 
+	unsigned long data2, unsigned long data3, unsigned char transparent)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_set_color_pattern(bgcolor, fgcolor, data0, data1, data2, data3, transparent);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_set_color_pattern(bgcolor, fgcolor, data0, data1, data2, data3, transparent);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_load_color_pattern_line
+ *---------------------------------------------------------------------------
+ */
+void gfx_load_color_pattern_line(short y, unsigned long *pattern_8x8)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_load_color_pattern_line(y, pattern_8x8);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_load_color_pattern_line(y, pattern_8x8);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_set_raster_operation
+ *---------------------------------------------------------------------------
+ */
+void gfx_set_raster_operation(unsigned char rop)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_set_raster_operation(rop);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_set_raster_operation(rop);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_pattern_fill
+ *---------------------------------------------------------------------------
+ */
+void gfx_pattern_fill(unsigned short x, unsigned short y, 
+	unsigned short width, unsigned short height)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_pattern_fill(x, y, width, height);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_pattern_fill(x, y, width, height);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_color_pattern_fill
+ *---------------------------------------------------------------------------
+ */
+void gfx_color_pattern_fill(unsigned short x, unsigned short y, 
+	unsigned short width, unsigned short height, unsigned long *pattern)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_color_pattern_fill(x, y, width, height, pattern);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_color_pattern_fill(x, y, width, height, pattern);
+#endif
+}
+	
+/*---------------------------------------------------------------------------
+ * gfx_screen_to_screen_blt
+ *---------------------------------------------------------------------------
+ */
+void gfx_screen_to_screen_blt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_screen_to_screen_blt(srcx, srcy, dstx, dsty, width, height);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_screen_to_screen_blt(srcx, srcy, dstx, dsty, width, height);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_screen_to_screen_xblt
+ *---------------------------------------------------------------------------
+ */
+void gfx_screen_to_screen_xblt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned long color)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_screen_to_screen_xblt(srcx, srcy, dstx, dsty, width, height, color);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_screen_to_screen_xblt(srcx, srcy, dstx, dsty, width, height, color);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_color_bitmap_to_screen_blt
+ *---------------------------------------------------------------------------
+ */
+void gfx_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned char *data, long pitch)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_color_bitmap_to_screen_blt(srcx, srcy, dstx, dsty, width, height,
+			data, pitch);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_color_bitmap_to_screen_blt(srcx, srcy, dstx, dsty, width, height,
+			data, pitch);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_color_bitmap_to_screen_xblt
+ *---------------------------------------------------------------------------
+ */
+void gfx_color_bitmap_to_screen_xblt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned char *data, long pitch, 
+	unsigned long color)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_color_bitmap_to_screen_xblt(srcx, srcy, dstx, dsty, width, height,
+			data, pitch, color);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_color_bitmap_to_screen_xblt(srcx, srcy, dstx, dsty, width, height,
+			data, pitch, color);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_mono_bitmap_to_screen_blt
+ *---------------------------------------------------------------------------
+ */
+void gfx_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy,
+	unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned char *data, short pitch)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_mono_bitmap_to_screen_blt(srcx, srcy, dstx, dsty, width, height,
+			data, pitch);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_mono_bitmap_to_screen_blt(srcx, srcy, dstx, dsty, width, height,
+			data, pitch);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_text_blt
+ *---------------------------------------------------------------------------
+ */
+void gfx_text_blt(unsigned short dstx, unsigned short dsty, unsigned short width, 
+	unsigned short height, unsigned char *data)
+
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_text_blt (dstx, dsty, width, height, data);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_text_blt (dstx, dsty, width, height, data);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_bresenham_line
+ *---------------------------------------------------------------------------
+ */
+void gfx_bresenham_line(unsigned short x, unsigned short y, 
+		unsigned short length, unsigned short initerr, 
+		unsigned short axialerr, unsigned short diagerr, 
+		unsigned short flags)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_bresenham_line(x, y, length, initerr, axialerr, diagerr, flags);
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_bresenham_line(x, y, length, initerr, axialerr, diagerr, flags);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_wait_until_idle
+ *---------------------------------------------------------------------------
+ */
+void gfx_wait_until_idle(void)
+{
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		gu1_wait_until_idle();
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu2_wait_until_idle();
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx_test_blt_pending
+ *---------------------------------------------------------------------------
+ */
+int gfx_test_blt_pending(void)
+{
+	int retval = 0;
+#if GFX_2DACCEL_GU1
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1)
+		retval = gu1_test_blt_pending();
+#endif
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		retval = gu2_test_blt_pending();
+#endif
+	return(retval);
+}
+
+/*---------------------------------------------------------------------------
+ * NEW ROUTINES FOR REDCLOUD
+ *---------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------
+ * gfx2_set_source_stride
+ *---------------------------------------------------------------------------
+ */
+void gfx2_set_source_stride(unsigned short stride)
+{
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu22_set_source_stride (stride);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx2_set_destination_stride
+ *---------------------------------------------------------------------------
+ */
+void gfx2_set_destination_stride(unsigned short stride)
+{
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu22_set_destination_stride (stride);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx2_set_pattern_origin
+ *---------------------------------------------------------------------------
+ */
+void gfx2_set_pattern_origin(int x, int y)
+{
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu22_set_pattern_origin (x, y);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx2_set_source_transparency
+ *---------------------------------------------------------------------------
+ */
+void gfx2_set_source_transparency(unsigned long color, unsigned long mask)
+{
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu22_set_source_transparency (color, mask);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx2_set_alpha_mode
+ *---------------------------------------------------------------------------
+ */
+void gfx2_set_alpha_mode(int mode)
+{
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu22_set_alpha_mode (mode);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx2_set_alpha_value
+ *---------------------------------------------------------------------------
+ */
+void gfx2_set_alpha_value(unsigned char value)
+{
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu22_set_alpha_value (value);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx2_pattern_fill
+ *---------------------------------------------------------------------------
+ */
+void gfx2_pattern_fill(unsigned long dstoffset, unsigned short width, 
+	unsigned short height)
+{
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu22_pattern_fill (dstoffset, width, height);
+#endif
+}
+
+/*---------------------------------------------------------------------------
+ * gfx2_color_pattern_fill
+ *---------------------------------------------------------------------------
+ */
+void gfx2_color_pattern_fill(unsigned long dstoffset, unsigned short width, 
+	unsigned short height, unsigned long *pattern)
+{
+#if GFX_2DACCEL_GU2
+	if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2)
+		gu22_color_pattern_fill (dstoffset, width, height, pattern);
+#endif
+}
+
+/*------